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Release v5.4.0
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‎LICENSE.md

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| rm_motor_speed<br>(pre-compiled libraries) | Renesas Electronics Corporation | [Renesas Software License Agreement](https://www.renesas.com/us/en/document/oth/disclaimer002)|
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| rm_zmod4xxx<br>(pre-compiled libraries) | Renesas Electronics Corporation | [Renesas Software License Agreement](https://www.renesas.com/us/en/document/oth/disclaimer002)|
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|<tr> <td colspan="3"><strong>Third-Party components included in the packs<strong></td></tr> |
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| [CMSIS](https://github.com/ARM-software/CMSIS_5) | ARM Limited | Apache-2.0 License |
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| [CMSIS](https://github.com/ARM-software/CMSIS_6) | ARM Limited | Apache-2.0 License |
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| [CMSIS Pack](https://github.com/Open-CMSIS-Pack) | ARM Limited | Apache-2.0 License |
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| [CMSIS DSP](https://github.com/ARM-software/CMSIS-DSP)| ARM Limited | Apache-2.0 License |
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| [CMSISNN](https://github.com/ARM-software/CMSIS-NN) | ARM Limited | Apache-2.0 License |

‎README.md

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### Current Release
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[FSP v5.3.0](https://github.com/renesas/fsp/releases/tag/v5.3.0)
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[FSP v5.4.0](https://github.com/renesas/fsp/releases/tag/v5.4.0)
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### Supported RA MCU Kits
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- FPB-RA2E3
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- FPB-RA4E1
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- FPB-RA4E2
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- FPB-RA4T1
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- FPB-RA6E1
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- FPB-RA6E2
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- FPB-RA6T3
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- EK-RA2A1
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- EK-RA2A2
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- EK-RA2E1
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#### For new users that are using FSP with e² studio
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1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.3.0).
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1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.4.0).
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2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required.
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#### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK ####

‎SUPPORTED_SOFTWARE.md

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‎ra/board/ra8d1_ek/board.h

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/* BSP Board Specific Includes. */
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#include "board_init.h"
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#include "board_sdram.h"
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#include "board_leds.h"
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#include "board_ethernet_phy.h"
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#include "../../src/bsp/mcu/all/board_sdram.h"
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/***********************************************************************************************************************
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* Macro definitions

‎ra/board/ra8d1_ek/board_sdram.c

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‎ra/fsp/inc/api/bsp_api.h

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#include "../../src/bsp/mcu/all/bsp_delay.h"
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#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
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#if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h")
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#include "../../src/bsp/mcu/all/internal/bsp_internal.h"
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#endif
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#endif
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/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */

‎ra/fsp/inc/api/r_cgc_api.h

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/** PLL clock output divisor. */
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typedef enum e_cgc_pll_out_div
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{
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CGC_PLL_OUT_DIV_2 = 2, ///< PLL output clock divided by 2
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CGC_PLL_OUT_DIV_3 = 3, ///< PLL output clock divided by 3
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CGC_PLL_OUT_DIV_4 = 4, ///< PLL output clock divided by 4
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CGC_PLL_OUT_DIV_5 = 5, ///< PLL output clock divided by 5
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CGC_PLL_OUT_DIV_6 = 6, ///< PLL output clock divided by 6
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CGC_PLL_OUT_DIV_8 = 8, ///< PLL output clock divided by 8
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CGC_PLL_OUT_DIV_9 = 9, ///< PLL output clock divided by 9
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CGC_PLL_OUT_DIV_16 = 16, ///< PLL output clock divided by 16
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CGC_PLL_OUT_DIV_2 = 2, ///< PLL output clock divided by 2
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CGC_PLL_OUT_DIV_3 = 3, ///< PLL output clock divided by 3
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CGC_PLL_OUT_DIV_4 = 4, ///< PLL output clock divided by 4
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CGC_PLL_OUT_DIV_5 = 5, ///< PLL output clock divided by 5
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CGC_PLL_OUT_DIV_6 = 6, ///< PLL output clock divided by 6
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CGC_PLL_OUT_DIV_8 = 8, ///< PLL output clock divided by 8
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CGC_PLL_OUT_DIV_9 = 9, ///< PLL output clock divided by 9
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CGC_PLL_OUT_DIV_1_5 = 10, ///< PLL output clock divided by 1.5
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CGC_PLL_OUT_DIV_16 = 16, ///< PLL output clock divided by 16
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} cgc_pll_out_div_t;
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#ifndef BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T

‎ra/fsp/inc/api/r_crc_api.h

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/** Structure for CRC inputs */
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typedef struct st_crc_input_t
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{
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uint32_t num_bytes; // Length of input buffer
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uint32_t crc_seed; // CRC seed value
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void * p_input_buffer; // Pointer to input buffer
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uint32_t num_bytes; ///< Length of input buffer. It must be 4-byte aligned when a 32-bit CRC polynomial function is used.
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uint32_t crc_seed; ///< CRC seed value
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const void * p_input_buffer; ///< Pointer to input buffer
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} crc_input_t;
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/** CRC control block. Allocate an instance specific control block to pass into the CRC API calls.

‎ra/fsp/inc/api/r_ether_api.h

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ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event
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ETHER_EVENT_LINK_ON, ///< Link up detection event
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ETHER_EVENT_LINK_OFF, ///< Link down detection event
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ETHER_EVENT_INTERRUPT, ///< Interrupt event
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ETHER_EVENT_INTERRUPT, ///< DEPRECATED Interrupt event
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ETHER_EVENT_RX_COMPLETE, ///< Receive complete event.
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ETHER_EVENT_RX_MESSAGE_LOST, ///< Receive FIFO overflow or Receive descriptor is full.
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ETHER_EVENT_TX_COMPLETE, ///< Transmit complete event.
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ETHER_EVENT_TX_BUFFER_EMPTY, ///< Transmit descriptor or FIFO is empty.
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ETHER_EVENT_TX_ABORTED, ///< Transmit abort event.
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ETHER_EVENT_ERR_GLOBAL, ///< Global error has occurred.
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} ether_event_t;
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#endif
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‎ra/fsp/inc/api/r_i2c_master_api.h

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{
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I2C_MASTER_EVENT_ABORTED = 1, ///< A transfer was aborted
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I2C_MASTER_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully
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I2C_MASTER_EVENT_TX_COMPLETE = 3 ///< A transmit operation was completed successfully
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I2C_MASTER_EVENT_TX_COMPLETE = 3, ///< A transmit operation was completed successfully
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I2C_MASTER_EVENT_START = 4, ///< I2C sent a start condition
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I2C_MASTER_EVENT_BYTE_ACK = 5, ///< I2C finished sending/receiving 1 data byte
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} i2c_master_event_t;
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/** I2C callback parameter definition */

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