Make all Xqci sub-extensions with 16/48-bit encodings dependent on Zca

Author: Derek Hower

cfgs/qc_iu/arch_overlay/ext/Xqci.yaml

@@ -87,6 +87,9 @@ Xqci:
     - [Xqcilo, "0.2.0"]
     - [Xqcilsm, "0.2.0"]
     - [Xqcisls, "0.2.0"]
+    requires:
+      name: Zca
+      version: ">= 1.0.0"
   description: |
     The Xqci extension includes a set of instructions that improve RISC-V code density and
     performance in microontrollers. It fills several gaps:

cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml

@@ -27,6 +27,7 @@ Xqciac:
     changes:
       - Add information about instruction formats of each instruction
       - Fix description and functionality of qc.shladd instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqciac extension includes three instructions to accelerate common
     address calculations.

cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml

@@ -26,6 +26,7 @@ Xqcibi:
       email: [email protected]
     changes:
       - Add information about instruction formats of each instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqcibi extension includes twelve conditional branch instructions that use an immediate
     operand for a source.

cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml

@@ -27,6 +27,7 @@ Xqcibm:
     changes:
       - Add information about instruction formats of each instruction
       - Fix description and functionality of qc.c.extu instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
     include insertion and extraction.

cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml

@@ -26,6 +26,7 @@ Xqcicm:
       email: [email protected]
     changes:
       - Add information about instruction formats of each instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqcicm extension includes thirteen conditional move instructions.
 

cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml

@@ -26,6 +26,7 @@ Xqciint:
       email: [email protected]
     changes:
       - Add information about instruction formats of each instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqciint extension includes eleven instructions to accelerate interrupt
     servicing by performing common actions during ISR prologue/epilogue.

cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml

@@ -26,6 +26,7 @@ Xqcilb:
       email: [email protected]
     changes:
       - Add information about instruction formats of each instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqcilb extension includes two 48-bit instructions to encode a long branch.
 

cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml

@@ -26,6 +26,7 @@ Xqcilia:
       email: [email protected]
     changes:
       - Add information about instruction formats of each instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqcilia extension includes eight 48-bit instructions that perform arithmetic using
     large immediates.

cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml

@@ -26,6 +26,7 @@ Xqcilo:
       email: [email protected]
     changes:
       - Add information about instruction formats of each instruction
+    requires: { name: Zca, version: ">= 1.0.0" }
   description: |
     The Xqcilo extension includes eight 48-bit load/stores instructions that use an offset
     larger than can be found in the base RISC-V ISA.