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Commit 0b95c63

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author
Derek Hower
committed
Merge branch 'main' into iu
2 parents 4ebcd4c + be96f79 commit 0b95c63

25 files changed

+999
-11
lines changed

‎arch/ext/I.yaml

+38-1
Original file line numberDiff line numberDiff line change
@@ -109,10 +109,47 @@ I:
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maximum: 127
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MISALIGNED_LDST:
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description: |
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Whether or not the implementation supports misaligned loads and stores in
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Whether or not the implementation supports non-atomic misaligned loads and stores in
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main memory (does *not* affect misaligned support to device memory)
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schema:
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type: boolean
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MISALIGNED_LDST_EXCEPTION_PRIORITY:
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description: |
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The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault
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or access-fault exceptions.
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May be one of:
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[separator="!"]
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!===
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! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.
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! low ! Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.
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!===
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MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE
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is non-zero, since the atomicity of an access cannot be determined in that case until after
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address translation.
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schema:
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type: string
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enum: ["high", "low"]
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extra_validation: |
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assert (MISALIGNED_LDST_EXCEPTION_PRIORITY == "low") if MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE.positive?
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MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE:
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description: |
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The maximum granule size, in bytes, that the hart can atomically perform a
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misligned load/store/AMO without raising a Misaligned exception. When MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE is 0, the hart
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cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can
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atomically load/store/AMO a misaligned access that is fully contained in a
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MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE-aligned region.
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[NOTE]
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Even if the hart is capable of performing a misligned load/store/AMO atomically,
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a misaligned exception may still occur if the access does not have the appropriate
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Misaligned Atomicity Granule PMA set.
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schema:
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type: integer
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# can't be larger than a page, since there is no way to reconcile that with virtual memory
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enum: [0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096]
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MISALIGNED_SPLIT_STRATEGY:
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description: |
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when misaligned accesses are supported, this determines the *order* in the implementation appears

‎arch/inst/A/amoadd.d.yaml

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@@ -0,0 +1,40 @@
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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amoadd.d:
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long_name: Atomic fetch-and-add doubleword
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description: |
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Atomically:
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* Load the doubleword at address _rs1_
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* Write the loaded value into _rd_
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* Add the value of register _rs2_ to the loaded value
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* Write the sum to the address in _rs1_
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definedBy: [A, Zaamo]
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base: 64
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assembly: xd, xs2, (xrs1)
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encoding:
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match: 00000------------011-----0101111
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variables:
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- name: aq
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location: 26
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- name: rl
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location: 27
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
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raise (ExceptionCode::IllegalInstruction, $encoding);
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}
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XReg virtual_address = X[rs1];
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X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Add, aq, rl);

‎arch/inst/A/amoadd.w.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amoadd.w:
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long_name: Atomic fetch-and-add word
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description: |
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Atomically:
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* Load the word at address _rs1_
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* Write the sign-extended value into _rd_
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* Add the least-significant word of register _rs2_ to the loaded value
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* Write the sum to the address in _rs1_
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definedBy: [A, Zaamo]
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assembly: xd, xs2, (xrs1)
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encoding:
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match: 00000------------010-----0101111
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variables:
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- name: aq
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location: 26
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- name: rl
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location: 27
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
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raise (ExceptionCode::IllegalInstruction, $encoding);
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}
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XReg virtual_address = X[rs1];
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X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Add, aq, rl);

‎arch/inst/A/amoand.d.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amoand.d:
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long_name: Atomic fetch-and-and doubleword
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description: |
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Atomically:
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* Load the doubleword at address _rs1_
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* Write the loaded value into _rd_
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* AND the value of register _rs2_ to the loaded value
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* Write the result to the address in _rs1_
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definedBy: [A, Zaamo]
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base: 64
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assembly: xd, xs2, (xrs1)
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encoding:
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match: 01100------------011-----0101111
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variables:
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- name: aq
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location: 26
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- name: rl
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location: 27
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
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raise (ExceptionCode::IllegalInstruction, $encoding);
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}
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XReg virtual_address = X[rs1];
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X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::And, aq, rl);

‎arch/inst/A/amoand.w.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amoand.w:
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long_name: Atomic fetch-and-and word
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description: |
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Atomically:
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* Load the word at address _rs1_
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* Write the sign-extended value into _rd_
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* AND the least-significant word of register _rs2_ to the loaded value
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* Write the result to the address in _rs1_
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definedBy: [A, Zaamo]
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assembly: xd, xs2, (xrs1)
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encoding:
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match: 01100------------010-----0101111
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variables:
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- name: aq
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location: 26
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- name: rl
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location: 27
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
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raise (ExceptionCode::IllegalInstruction, $encoding);
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}
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XReg virtual_address = X[rs1];
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X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::And, aq, rl);

‎arch/inst/A/amomax.d.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amomax.d:
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long_name: Atomic MAX doubleword
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description: |
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Atomically:
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* Load the doubleword at address _rs1_
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* Write the loaded value into _rd_
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* Signed compare the value of register _rs2_ to the loaded value, and select the maximum value
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* Write the maximum to the address in _rs1_
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definedBy: [A, Zaamo]
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base: 64
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assembly: xd, xs2, (xrs1)
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encoding:
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match: 10100------------011-----0101111
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variables:
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- name: aq
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location: 26
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- name: rl
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location: 27
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
35+
raise (ExceptionCode::IllegalInstruction, $encoding);
36+
}
37+
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XReg virtual_address = X[rs1];
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X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Max, aq, rl);

‎arch/inst/A/amomax.w.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amomax.w:
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long_name: Atomic MAX word
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description: |
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Atomically:
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* Load the word at address _rs1_
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* Write the sign-extended value into _rd_
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* Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value
11+
* Write the maximum to the address in _rs1_
12+
definedBy: [A, Zaamo]
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assembly: xd, xs2, (xrs1)
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encoding:
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match: 10100------------010-----0101111
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variables:
17+
- name: aq
18+
location: 26
19+
- name: rl
20+
location: 27
21+
- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
25+
- name: rd
26+
location: 11-7
27+
access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
33+
if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
34+
raise (ExceptionCode::IllegalInstruction, $encoding);
35+
}
36+
37+
XReg virtual_address = X[rs1];
38+
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X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Max, aq, rl);

‎arch/inst/A/amomaxu.d.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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amomaxu.d:
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long_name: Atomic MAX unsigned doubleword
5+
description: |
6+
Atomically:
7+
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* Load the doubleword at address _rs1_
9+
* Write the loaded value into _rd_
10+
* Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value
11+
* Write the maximum to the address in _rs1_
12+
definedBy: [A, Zaamo]
13+
base: 64
14+
assembly: xd, xs2, (xrs1)
15+
encoding:
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match: 11100------------011-----0101111
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variables:
18+
- name: aq
19+
location: 26
20+
- name: rl
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location: 27
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
34+
if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
35+
raise (ExceptionCode::IllegalInstruction, $encoding);
36+
}
37+
38+
XReg virtual_address = X[rs1];
39+
40+
X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Maxu, aq, rl);

‎arch/inst/A/amomaxu.w.yaml

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
amomaxu.w:
4+
long_name: Atomic MAX unsigned word
5+
description: |
6+
Atomically:
7+
8+
* Load the word at address _rs1_
9+
* Write the sign-extended value into _rd_
10+
* Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value
11+
* Write the maximum to the address in _rs1_
12+
definedBy: [A, Zaamo]
13+
assembly: xd, xs2, (xrs1)
14+
encoding:
15+
match: 11100------------010-----0101111
16+
variables:
17+
- name: aq
18+
location: 26
19+
- name: rl
20+
location: 27
21+
- name: rs2
22+
location: 24-20
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- name: rs1
24+
location: 19-15
25+
- name: rd
26+
location: 11-7
27+
access:
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s: always
29+
u: always
30+
vs: always
31+
vu: always
32+
operation(): |
33+
if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
34+
raise (ExceptionCode::IllegalInstruction, $encoding);
35+
}
36+
37+
XReg virtual_address = X[rs1];
38+
39+
X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Maxu, aq, rl);

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