|
22 | 22 | "index": "1,1,1,1",
|
23 | 23 | "lanes": "65,66,67,68",
|
24 | 24 | "alias_at_lanes": "Eth1/1, Eth1/2, Eth1/3, Eth1/4",
|
25 |
| - "breakout_modes": "1x100G[40G],2x50G,4x25G[10G]" |
| 25 | + "breakout_modes": { |
| 26 | + "1x100G[40G]": ["Eth1"], |
| 27 | + "2x50G": ["Eth1/1", "Eth1/3"], |
| 28 | + "4x25G[10G]": ["Eth1/1", "Eth1/2", "Eth1/3", "Eth1/4"] |
| 29 | + } |
26 | 30 | },
|
27 | 31 | "Ethernet4": {
|
28 | 32 | "index": "2,2,2,2",
|
29 | 33 | "lanes": "69,70,71,72",
|
30 | 34 | "alias_at_lanes": "Eth2/1, Eth2/2, Eth2/3, Eth2/4",
|
31 |
| - "breakout_modes": "1x100G[40G],2x50G,4x25G[10G],1x50G(2)+2x25G(2)" |
| 35 | + "breakout_modes": { |
| 36 | + "1x100G[40G]": ["Eth2"], |
| 37 | + "2x50G": ["Eth2/1", "Eth2/3"], |
| 38 | + "4x25G[10G]": ["Eth2/1", "Eth2/2", "Eth2/3", "Eth2/4"], |
| 39 | + "1x50G(2)+2x25G(2)": ["Eth2/1", "Eth2/3", "Eth2/4"] |
| 40 | + } |
32 | 41 | },
|
33 | 42 | "Ethernet8": {
|
34 | 43 | "index": "3,3,3,3",
|
35 | 44 | "lanes": "73,74,75,76",
|
36 | 45 | "alias_at_lanes": "Eth3/1, Eth3/2, Eth3/3, Eth3/4",
|
37 |
| - "breakout_modes": "1x100G[40G],2x50G,4x25G[10G],1x50G(2)+2x25G(2)" |
| 46 | + "breakout_modes": { |
| 47 | + "1x100G[40G]": ["Eth3"], |
| 48 | + "2x50G": ["Eth3/1", "Eth3/3"], |
| 49 | + "4x25G[10G]": ["Eth3/1", "Eth3/2", "Eth3/3", "Eth3/4"], |
| 50 | + "1x50G(2)+2x25G(2)": ["Eth3/1", "Eth3/3", "Eth3/4"] |
| 51 | + } |
38 | 52 | },
|
39 | 53 | "Ethernet12": {
|
40 | 54 | "index": "4,4,4,4",
|
41 | 55 | "lanes": "77,78,79,80",
|
42 | 56 | "alias_at_lanes": "Eth4/1, Eth4/2, Eth4/3, Eth4/4",
|
43 |
| - "breakout_modes": "1x100G[40G],2x50G,4x25G[10G]" |
| 57 | + "breakout_modes": { |
| 58 | + "1x100G[40G]": ["Eth4"], |
| 59 | + "2x50G": ["Eth4/1", "Eth4/3"], |
| 60 | + "4x25G[10G]": ["Eth4/1", "Eth4/2", "Eth4/3", "Eth4/4"] |
| 61 | + } |
44 | 62 | }
|
45 | 63 | }
|
46 | 64 | }
|
|
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