Do not touch pre-existing modules loaded into Yosys

Author: povik

src/slang_frontend.cc

@@ -3395,6 +3395,8 @@ struct SlangFrontend : Frontend {
 		(void) filename;
 		log_header(design, "Executing SLANG frontend.\n");
 
+		// names of RTLIL modules added in this invocation; does not include blackboxes
+		std::vector<RTLIL::IdString> emitted_module_names;
 		slang::driver::Driver driver;
 		driver.addStandardArgs();
 		SynthesisSettings settings;
@@ -3480,6 +3482,7 @@ struct SlangFrontend : Frontend {
 
 			for (int i = 0; i < (int) hqueue.queue.size(); i++) {
 				NetlistContext &netlist = *hqueue.queue[i];
+				emitted_module_names.push_back(netlist.canvas->name);
 
 				if (netlist.disabled)
 					continue;
@@ -3515,6 +3518,11 @@ struct SlangFrontend : Frontend {
 		}
 
 		if (!settings.no_proc.value_or(false)) {
+			RTLIL::Selection emitted_modules = RTLIL::Selection::EmptySelection(design);
+			for (auto name : emitted_module_names)
+				emitted_modules.selected_modules.insert(name);
+			design->push_selection(emitted_modules);
+
 			log_push();
 			call(design, "undriven");
 			call(design, "proc_clean");
@@ -3527,6 +3535,8 @@ struct SlangFrontend : Frontend {
 			call(design, "proc_clean");
 			call(design, "opt_expr -keepdc");
 			log_pop();
+
+			design->pop_selection();
 		}
 	}
 } SlangFrontend;

src/slang_frontend.h

@@ -473,8 +473,8 @@ struct NetlistContext : RTLILBuilder, public DiagnosticIssuer {
 	Yosys::dict<const ast::Symbol*, RTLIL::Wire *> wire_cache;
 
 	// With this flag set we will not elaborate this netlist; we set this when
-	// `scopes_remap` is incomplete due to errors in processing the instantiation
-	// of `realm` somewhere in the input.
+	// `scopes_remap` is incomplete due to errors in processing an instantiation
+	// of `realm`.
 	bool disabled = false;
 
 	NetlistContext(RTLIL::Design *design,

tests/CMakeLists.txt

@@ -38,6 +38,7 @@ set(ALL_TESTS
     various/intf_array_naming.ys
     various/intf_w_hierarchy.ys
     various/issue142.ys
+    various/issue208.ys
     various/issue50.ys
     various/mem_inference.ys
     various/meminit.ys

tests/various/issue208.ys

@@ -0,0 +1,22 @@
+read_verilog <<EOF
+module primi(d, q, clk);
+input wire clk;
+input wire d;
+output reg q;
+always @(posedge clk)
+	q <= d;
+endmodule
+EOF
+
+read_slang <<EOF
+(*blackbox*)
+module primi(d, q, clk);
+input wire clk;
+input wire d;
+output reg q;
+endmodule
+
+module top(input logic clk, input logic d, output logic q);
+	primi inst(.*);
+endmodule
+EOF