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Always signal when comparing with signalling NaN
Follows up on discussion in #164. Previously, comparisons with signalling NaN would set `FPCSR[IVF]` only for ordered/unordered EQ/NE. Now, all comparisons set this flag when operating on a signalling NaN. Updated formal verification of `pfpu_cmp` to match.
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+4
-31
lines changed

3 files changed

+4
-31
lines changed

bench/formal/Makefile

+1-2
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,7 @@ TESTS := mor1kx_cache_lru \
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BROKEN_TESTS := \
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mor1kx_lsu_cappuccino \
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mor1kx_cpu_cappuccino \
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mor1kx \
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pfpu32_cmp_snan_bug
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mor1kx
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all: $(TESTS)
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clean:

bench/formal/pfpu32_cmp_snan_bug.sby

-17
This file was deleted.

rtl/verilog/pfpu32/pfpu32_cmp.v

+3-12
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@@ -102,9 +102,9 @@ wire eqne = (generic_cmp_opc_i == GENERIC_SFEQ) |
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(generic_cmp_opc_i == GENERIC_SFNE);
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// Comparison is invalid if:
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// 1) sNaN is an operand of ordered/unordered EQ/NE comparison
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// 1) sNaN is an operand of any comparison
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// 2) NaN is an operand of ordered LT/LE/GT/GE comparison
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wire inv_cmp = (eqne & snan) | ((~eqne) & anan & (~unordered_cmp_bit_i));
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wire inv_cmp = snan | ((~eqne) & anan & (~unordered_cmp_bit_i));
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////////////////////////////////////////////////////////////////////////
@@ -383,16 +383,7 @@ assign ready_o = fpu_op_is_comp_i;
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if (fpu_op_is_comp_i) begin
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assert (cmp_flag_o == f_cmp_flag);
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`ifndef PFPU32_FCMP_SNAN_BUG
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// XXX inv_o diverges from expected behaviour when sNaN is passed to
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// sfult, sfule, sfugt, or sfuge.
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if (~(f_have_snan & unordered_cmp_bit_i
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& (generic_cmp_opc_i == GENERIC_SFLT
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| generic_cmp_opc_i == GENERIC_SFLE
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| generic_cmp_opc_i == GENERIC_SFGT
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| generic_cmp_opc_i == GENERIC_SFGE)))
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`endif // PFPU32_FCMP_SNAN_BUG
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assert (inv_o == f_have_inv);
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assert (inv_o == f_have_inv);
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assert (inf_o == f_have_inf);
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end
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end

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