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| 1 | +From 342f0dd9b4f9fc49dcb589cd98933ea330de55d8 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Aurelien Jarno < [email protected]> |
| 3 | +Date: Thu, 4 Jan 2024 11:30:34 +0100 |
| 4 | +Subject: [PATCH] RISC-V: use RDTIME instead of RDCYCLE |
| 5 | + |
| 6 | +Starting with Linux 6.6 [1], RDCYCLE is a privileged instruction on |
| 7 | +RISC-V and can't be used directly from userland. There is a sysctl |
| 8 | +option to change that as a transition period, but it will eventually |
| 9 | +disappear. |
| 10 | + |
| 11 | +Use RDTIME instead, which while less accurate has the advantage of being |
| 12 | +synchronized between CPU (and thus monotonic) and of constant frequency. |
| 13 | + |
| 14 | +[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cc4c07c89aada16229084eeb93895c95b7eabaa3 |
| 15 | + |
| 16 | +Upstream-Status: Backport [https://github.com/MariaDB/server/commit/656f8867720efc1b4dd0969319f35a3e1a2a005e] |
| 17 | +Signed-off-by: Changqing Li < [email protected]> |
| 18 | +--- |
| 19 | + include/my_rdtsc.h | 12 ++++++------ |
| 20 | + 1 file changed, 6 insertions(+), 6 deletions(-) |
| 21 | + |
| 22 | +diff --git a/include/my_rdtsc.h b/include/my_rdtsc.h |
| 23 | +index 8b9b0046bc0..21e44847d9a 100644 |
| 24 | +--- a/include/my_rdtsc.h |
| 25 | ++++ b/include/my_rdtsc.h |
| 26 | +@@ -111,7 +111,7 @@ C_MODE_START |
| 27 | + On AARCH64, we use the generic timer base register. We override clang |
| 28 | + implementation for aarch64 as it access a PMU register which is not |
| 29 | + guaranteed to be active. |
| 30 | +- On RISC-V, we use the rdcycle instruction to read from mcycle register. |
| 31 | ++ On RISC-V, we use the rdtime instruction to read from mtime register. |
| 32 | + |
| 33 | + Sadly, we have nothing for the Digital Alpha, MIPS, Motorola m68k, |
| 34 | + HP PA-RISC or other non-mainstream (or obsolete) processors. |
| 35 | +@@ -211,15 +211,15 @@ static inline ulonglong my_timer_cycles(void) |
| 36 | + } |
| 37 | + #elif defined(__riscv) |
| 38 | + #define MY_TIMER_ROUTINE_CYCLES MY_TIMER_ROUTINE_RISCV |
| 39 | +- /* Use RDCYCLE (and RDCYCLEH on riscv32) */ |
| 40 | ++ /* Use RDTIME (and RDTIMEH on riscv32) */ |
| 41 | + { |
| 42 | + # if __riscv_xlen == 32 |
| 43 | + ulong result_lo, result_hi0, result_hi1; |
| 44 | + /* Implemented in assembly because Clang insisted on branching. */ |
| 45 | + __asm __volatile__( |
| 46 | +- "rdcycleh %0\n" |
| 47 | +- "rdcycle %1\n" |
| 48 | +- "rdcycleh %2\n" |
| 49 | ++ "rdtimeh %0\n" |
| 50 | ++ "rdtime %1\n" |
| 51 | ++ "rdtimeh %2\n" |
| 52 | + "sub %0, %0, %2\n" |
| 53 | + "seqz %0, %0\n" |
| 54 | + "sub %0, zero, %0\n" |
| 55 | +@@ -228,7 +228,7 @@ static inline ulonglong my_timer_cycles(void) |
| 56 | + return (static_cast<ulonglong>(result_hi1) << 32) | result_lo; |
| 57 | + # else |
| 58 | + ulonglong result; |
| 59 | +- __asm __volatile__("rdcycle %0" : "=r"(result)); |
| 60 | ++ __asm __volatile__("rdtime %0" : "=r"(result)); |
| 61 | + return result; |
| 62 | + } |
| 63 | + # endif |
| 64 | +-- |
| 65 | +2.25.1 |
| 66 | + |
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