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alfredfoolofk
alfredfo
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olofk
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boilerplate for external interrupts
Signed-off-by: Alfred Persson Forsberg <[email protected]>
1 parent f6116cf commit cb57969

40 files changed

+1580
-83
lines changed

‎.github/workflows/lint.yml

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,9 @@ on: [push, pull_request]
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jobs:
66
lint:
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runs-on: ubuntu-latest
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strategy:
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matrix:
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width: [1, 4]
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name: Linter
912
env:
1013
REPO : serv
@@ -17,6 +20,6 @@ jobs:
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- run: sudo apt install verilator
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- run: pip3 install fusesoc
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- run: fusesoc library add $REPO $GITHUB_WORKSPACE/$REPO
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- run: fusesoc run --target=lint $VLNV
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- run: fusesoc run --target=lint servant
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- run: fusesoc run --target=lint $VLNV --W=${{ matrix.width }}
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- run: fusesoc run --target=lint servant --width=${{ matrix.width }}
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- run: fusesoc run --target=lint serving

‎bench/decoder_sim.v

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`default_nettype none
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module decoder_sim
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(input wire wb_clk,
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input wire [31:2] wb_rdt,
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input wire wb_en,
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output wire ebreak,
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output wire jal_or_jalr,
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output wire mret,
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output wire wfi,
10+
output wire sh_right,
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output wire bne_or_bge,
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output wire cond_branch,
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output wire e_op,
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output wire branch_op,
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output wire shift_op,
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output wire slt_or_branch,
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output wire rd_op,
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output wire two_stage_op,
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output wire dbus_en,
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output wire mdu_op,
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output wire [2:0] ext_funct3,
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output wire bufreg_rs1_en,
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output wire bufreg_imm_en,
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output wire bufreg_clr_lsb,
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output wire bufreg_sh_signed,
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output wire ctrl_utype,
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output wire ctrl_pc_rel,
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output wire alu_sub,
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output wire [1:0] alu_bool_op,
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output wire alu_cmp_eq,
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output wire alu_cmp_sig,
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output wire [2:0] alu_rd_sel,
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output wire mem_signed,
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output wire mem_word,
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output wire mem_half,
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output wire mem_cmd,
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output wire csr_en,
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output wire [1:0] csr_addr,
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output wire csr_mstatus_en,
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output wire csr_mie_en,
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output wire csr_mcause_en,
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output wire [1:0] csr_source,
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output wire csr_d_sel,
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output wire csr_imm_en,
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output wire mtval_pc,
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output wire [3:0] immdec_ctrl,
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output wire [3:0] immdec_en,
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output wire op_b_source,
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output wire rd_mem_en,
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output wire rd_csr_en,
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output wire rd_alu_en
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);
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// Instantiate the DUT
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serv_decode
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#(.PRE_REGISTER (1),
57+
.MDU (0))
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dut (
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.clk(wb_clk),
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.i_wb_rdt(wb_rdt),
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.i_wb_en(wb_en),
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// Outputs
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.o_sh_right(sh_right),
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.o_bne_or_bge(bne_or_bge),
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.o_cond_branch(cond_branch),
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.o_e_op(e_op),
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.o_ebreak(ebreak),
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.o_wfi(wfi),
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.o_branch_op(branch_op),
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.o_shift_op(shift_op),
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.o_rd_op(rd_op),
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.o_two_stage_op(two_stage_op),
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.o_dbus_en(dbus_en),
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.o_mdu_op(mdu_op),
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.o_ext_funct3(ext_funct3),
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.o_bufreg_rs1_en(bufreg_rs1_en),
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.o_bufreg_imm_en(bufreg_imm_en),
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.o_bufreg_clr_lsb(bufreg_clr_lsb),
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.o_bufreg_sh_signed(bufreg_sh_signed),
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.o_ctrl_jal_or_jalr(jal_or_jalr),
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.o_ctrl_utype(ctrl_utype),
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.o_ctrl_pc_rel(ctrl_pc_rel),
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.o_ctrl_mret(mret),
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.o_alu_sub(alu_sub),
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.o_alu_bool_op(alu_bool_op),
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.o_alu_cmp_eq(alu_cmp_eq),
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.o_alu_cmp_sig(alu_cmp_sig),
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.o_alu_rd_sel(alu_rd_sel),
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.o_mem_signed(mem_signed),
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.o_mem_word(mem_word),
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.o_mem_half(mem_half),
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.o_mem_cmd(mem_cmd),
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.o_csr_en(csr_en),
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.o_csr_addr(csr_addr),
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.o_csr_mstatus_en(csr_mstatus_en),
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.o_csr_mie_en(csr_mie_en),
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.o_csr_mcause_en(csr_mcause_en),
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.o_csr_source(csr_source),
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.o_csr_d_sel(csr_d_sel),
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.o_csr_imm_en(csr_imm_en),
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.o_mtval_pc(mtval_pc),
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.o_immdec_ctrl(immdec_ctrl),
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.o_immdec_en(immdec_en),
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.o_op_b_source(op_b_source),
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.o_rd_mem_en(rd_mem_en),
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.o_rd_csr_en(rd_csr_en),
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.o_rd_alu_en(rd_alu_en)
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);
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endmodule

‎bench/decoder_tb.cpp

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#include <fcntl.h>
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#include <cstdint>
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#include <csignal>
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#include <iostream>
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#include <fstream>
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#include <memory>
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#include <ctime>
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#include <string>
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#include "verilated_vcd_c.h"
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#include "Vdecoder_sim.h"
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void INThandler(int signal) {
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std::cout << "\nCaught ctrl-c\n";
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std::exit(0);
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}
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void test_instruction(Vdecoder_sim *top, const std::string& instr_name, uint32_t instr);
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void cycle(Vdecoder_sim *top);
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int main(int argc, char** argv, char** env) {
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Verilated::commandArgs(argc, argv);
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Vdecoder_sim *top = new Vdecoder_sim;
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std::signal(SIGINT, INThandler);
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top->wb_clk = 0;
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top->wb_rdt = 0;
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top->wb_en = 0;
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std::cout << "Testing decoder\n";
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test_instruction(top, "jalr", 0x0000006F);
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test_instruction(top, "mret", 0x30200073);
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test_instruction(top, "ebreak", 0x00100073);
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test_instruction(top, "wfi", 0x10500073);
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test_instruction(top, "add", 0x00000033);
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test_instruction(top, "addi", 0x00000013);
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test_instruction(top, "sub", 0x40000033);
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test_instruction(top, "and", 0x00007033);
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test_instruction(top, "andi", 0x00007013);
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test_instruction(top, "or", 0x00006033);
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test_instruction(top, "ori", 0x00006013);
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test_instruction(top, "xor", 0x00004033);
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test_instruction(top, "xori", 0x00004013);
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test_instruction(top, "sll", 0x00001033);
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test_instruction(top, "slli", 0x00001013);
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test_instruction(top, "srl", 0x00005033);
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test_instruction(top, "srli", 0x00005013);
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test_instruction(top, "sra", 0x40005033);
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test_instruction(top, "srai", 0x40005013);
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test_instruction(top, "lui", 0x00000037);
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test_instruction(top, "auipc", 0x00000017);
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test_instruction(top, "lw", 0x00002003);
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test_instruction(top, "lh", 0x00001003);
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test_instruction(top, "lhu", 0x00005003);
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test_instruction(top, "lb", 0x00000003);
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test_instruction(top, "lbu", 0x00004003);
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test_instruction(top, "sw", 0x00002023);
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test_instruction(top, "sh", 0x00001023);
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test_instruction(top, "sb", 0x00000023);
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test_instruction(top, "jal", 0x0000006F);
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test_instruction(top, "jalr", 0x00000067);
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test_instruction(top, "beq", 0x00000063);
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test_instruction(top, "bne", 0x00001063);
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test_instruction(top, "blt", 0x00004063);
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test_instruction(top, "bge", 0x00005063);
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test_instruction(top, "bltu", 0x00006063);
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test_instruction(top, "bgeu", 0x00007063);
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test_instruction(top, "slt", 0x00002033);
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test_instruction(top, "slti", 0x00002013);
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test_instruction(top, "sltu", 0x00003033);
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test_instruction(top, "sltiu", 0x00003013);
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test_instruction(top, "ecall", 0x00000073);
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test_instruction(top, "ebreak", 0x00100073);
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test_instruction(top, "fence", 0x0000000F);
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test_instruction(top, "fence.i", 0x0000100F);
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test_instruction(top, "csrrw", 0x00001073);
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test_instruction(top, "csrrs", 0x00002073);
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test_instruction(top, "csrrc", 0x00003073);
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test_instruction(top, "csrrwi", 0x00005073);
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test_instruction(top, "csrrsi", 0x00006073);
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test_instruction(top, "csrrci", 0x00007073);
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return 0;
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}
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void cycle(Vdecoder_sim *top) {
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top->eval();
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top->wb_clk = 0;
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top->eval();
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top->wb_clk = 1;
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top->eval();
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}
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void test_instruction(Vdecoder_sim *top, const std::string& instr_name, uint32_t instr) {
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std::ofstream outfile(instr_name + ".txt");
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std::cout << "Testing " << instr_name << "\n";
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outfile << "Testing " << instr_name << "\n";
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top->wb_rdt = instr >> 2;
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top->wb_en = 1;
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cycle(top);
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outfile << "jal_or_jalr: " << std::to_string(top->jal_or_jalr) << std::endl;
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outfile << "ebreak: " << std::to_string(top->ebreak) << std::endl;
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outfile << "mret: " << std::to_string(top->mret) << std::endl;
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outfile << "wfi: " << std::to_string(top->wfi) << std::endl;
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outfile << "sh_right: " << std::to_string(top->sh_right) << std::endl;
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outfile << "bne_or_bge: " << std::to_string(top->bne_or_bge) << std::endl;
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outfile << "cond_branch: " << std::to_string(top->cond_branch) << std::endl;
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outfile << "e_op: " << std::to_string(top->e_op) << std::endl;
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outfile << "branch_op: " << std::to_string(top->branch_op) << std::endl;
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outfile << "shift_op: " << std::to_string(top->shift_op) << std::endl;
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outfile << "slt_or_branch: " << std::to_string(top->slt_or_branch) << std::endl;
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outfile << "rd_op: " << std::to_string(top->rd_op) << std::endl;
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outfile << "two_stage_op: " << std::to_string(top->two_stage_op) << std::endl;
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outfile << "dbus_en: " << std::to_string(top->dbus_en) << std::endl;
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outfile << "mdu_op: " << std::to_string(top->mdu_op) << std::endl;
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outfile << "ext_funct3: " << std::to_string(top->ext_funct3) << std::endl;
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outfile << "bufreg_rs1_en: " << std::to_string(top->bufreg_rs1_en) << std::endl;
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outfile << "bufreg_imm_en: " << std::to_string(top->bufreg_imm_en) << std::endl;
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outfile << "bufreg_clr_lsb: " << std::to_string(top->bufreg_clr_lsb) << std::endl;
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outfile << "bufreg_sh_signed: " << std::to_string(top->bufreg_sh_signed) << std::endl;
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outfile << "ctrl_utype: " << std::to_string(top->ctrl_utype) << std::endl;
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outfile << "ctrl_pc_rel: " << std::to_string(top->ctrl_pc_rel) << std::endl;
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outfile << "alu_sub: " << std::to_string(top->alu_sub) << std::endl;
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outfile << "alu_bool_op: " << std::to_string(top->alu_bool_op) << std::endl;
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outfile << "alu_cmp_eq: " << std::to_string(top->alu_cmp_eq) << std::endl;
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outfile << "alu_cmp_sig: " << std::to_string(top->alu_cmp_sig) << std::endl;
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outfile << "alu_rd_sel: " << std::to_string(top->alu_rd_sel) << std::endl;
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outfile << "mem_signed: " << std::to_string(top->mem_signed) << std::endl;
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outfile << "mem_word: " << std::to_string(top->mem_word) << std::endl;
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outfile << "mem_half: " << std::to_string(top->mem_half) << std::endl;
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outfile << "mem_cmd: " << std::to_string(top->mem_cmd) << std::endl;
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outfile << "csr_en: " << std::to_string(top->csr_en) << std::endl;
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outfile << "csr_addr: " << std::to_string(top->csr_addr) << std::endl;
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outfile << "csr_mstatus_en: " << std::to_string(top->csr_mstatus_en) << std::endl;
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outfile << "csr_mie_en: " << std::to_string(top->csr_mie_en) << std::endl;
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outfile << "csr_mcause_en: " << std::to_string(top->csr_mcause_en) << std::endl;
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outfile << "csr_source: " << std::to_string(top->csr_source) << std::endl;
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outfile << "csr_d_sel: " << std::to_string(top->csr_d_sel) << std::endl;
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outfile << "csr_imm_en: " << std::to_string(top->csr_imm_en) << std::endl;
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outfile << "mtval_pc: " << std::to_string(top->mtval_pc) << std::endl;
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outfile << "immdec_ctrl: " << std::to_string(top->immdec_ctrl) << std::endl;
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outfile << "immdec_en: " << std::to_string(top->immdec_en) << std::endl;
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outfile << "op_b_source: " << std::to_string(top->op_b_source) << std::endl;
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outfile << "rd_mem_en: " << std::to_string(top->rd_mem_en) << std::endl;
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outfile << "rd_csr_en: " << std::to_string(top->rd_csr_en) << std::endl;
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outfile << "rd_alu_en: " << std::to_string(top->rd_alu_en) << std::endl;
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assert(!(top->wfi && instr_name != "wfi"));
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top->wb_en = 0;
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cycle(top);
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outfile.close();
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}

‎bench/servant_external_sim.v

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`default_nettype none
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module servant_external_sim
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(input wire wb_clk,
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input wire wb_rst,
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input wire ext_irq,
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output wire [31:0] pc_adr,
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output wire pc_vld,
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output wire q,
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output wire mret
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);
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parameter memfile = "";
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parameter memsize = 8192;
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parameter width = 1;
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parameter with_csr = 1;
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parameter compressed = 0;
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parameter align = compressed;
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parameter interrupt_time = 3000;
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reg [1023:0] firmware_file;
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initial
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if ($value$plusargs("firmware=%s", firmware_file)) begin
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$display("Loading RAM from %0s", firmware_file);
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$readmemh(firmware_file, dut.servant.ram.mem);
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end
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servant_sleep_dummy
28+
#(.memfile (memfile),
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.memsize (memsize),
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.width (width),
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.debug (1'b1),
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.sim (1),
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.with_csr (with_csr),
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.compress (compressed[0:0]),
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.align (align[0:0]))
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dut(wb_clk, wb_rst, ext_irq, q);
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assign pc_adr = dut.servant.wb_mem_adr;
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assign pc_vld = dut.servant.wb_mem_ack;
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assign mret = dut.servant.cpu.cpu.mret;
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endmodule

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