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‎drivers/arm/i2c_master.c

Lines changed: 53 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -34,98 +34,83 @@ static uint8_t i2c_address;
3434

3535
static const I2CConfig i2cconfig = {
3636
#ifdef USE_I2CV1
37-
I2C1_OPMODE,
38-
I2C1_CLOCK_SPEED,
39-
I2C1_DUTY_CYCLE,
37+
I2C1_OPMODE,
38+
I2C1_CLOCK_SPEED,
39+
I2C1_DUTY_CYCLE,
4040
#else
41-
STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) |
42-
STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) |
43-
STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL),
44-
0,
45-
0
41+
STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) | STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) | STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL), 0, 0
4642
#endif
4743
};
4844

4945
static i2c_status_t chibios_to_qmk(const msg_t* status) {
50-
switch (*status) {
51-
case I2C_NO_ERROR:
52-
return I2C_STATUS_SUCCESS;
53-
case I2C_TIMEOUT:
54-
return I2C_STATUS_TIMEOUT;
55-
// I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
56-
default:
57-
return I2C_STATUS_ERROR;
58-
}
46+
switch (*status) {
47+
case I2C_NO_ERROR:
48+
return I2C_STATUS_SUCCESS;
49+
case I2C_TIMEOUT:
50+
return I2C_STATUS_TIMEOUT;
51+
// I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
52+
default:
53+
return I2C_STATUS_ERROR;
54+
}
5955
}
6056

61-
__attribute__ ((weak))
62-
void i2c_init(void)
63-
{
64-
// Try releasing special pins for a short time
65-
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
66-
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
57+
__attribute__((weak)) void i2c_init(void) {
58+
// Try releasing special pins for a short time
59+
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
60+
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
6761

68-
chThdSleepMilliseconds(10);
62+
chThdSleepMilliseconds(10);
6963

7064
#ifdef USE_I2CV1
71-
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
72-
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
65+
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
66+
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
7367
#else
74-
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
75-
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
68+
palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
69+
palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
7670
#endif
7771

78-
//i2cInit(); //This is invoked by halInit() so no need to redo it.
72+
// i2cInit(); //This is invoked by halInit() so no need to redo it.
7973
}
8074

81-
i2c_status_t i2c_start(uint8_t address)
82-
{
83-
i2c_address = address;
84-
i2cStart(&I2C_DRIVER, &i2cconfig);
85-
return I2C_STATUS_SUCCESS;
75+
i2c_status_t i2c_start(uint8_t address) {
76+
i2c_address = address;
77+
i2cStart(&I2C_DRIVER, &i2cconfig);
78+
return I2C_STATUS_SUCCESS;
8679
}
8780

88-
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout)
89-
{
90-
i2c_address = address;
91-
i2cStart(&I2C_DRIVER, &i2cconfig);
92-
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
93-
return chibios_to_qmk(&status);
81+
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
82+
i2c_address = address;
83+
i2cStart(&I2C_DRIVER, &i2cconfig);
84+
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
85+
return chibios_to_qmk(&status);
9486
}
9587

96-
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
97-
{
98-
i2c_address = address;
99-
i2cStart(&I2C_DRIVER, &i2cconfig);
100-
msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
101-
return chibios_to_qmk(&status);
88+
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
89+
i2c_address = address;
90+
i2cStart(&I2C_DRIVER, &i2cconfig);
91+
msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
92+
return chibios_to_qmk(&status);
10293
}
10394

104-
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout)
105-
{
106-
i2c_address = devaddr;
107-
i2cStart(&I2C_DRIVER, &i2cconfig);
95+
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
96+
i2c_address = devaddr;
97+
i2cStart(&I2C_DRIVER, &i2cconfig);
10898

109-
uint8_t complete_packet[length + 1];
110-
for(uint8_t i = 0; i < length; i++)
111-
{
112-
complete_packet[i+1] = data[i];
113-
}
114-
complete_packet[0] = regaddr;
99+
uint8_t complete_packet[length + 1];
100+
for (uint8_t i = 0; i < length; i++) {
101+
complete_packet[i + 1] = data[i];
102+
}
103+
complete_packet[0] = regaddr;
115104

116-
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
117-
return chibios_to_qmk(&status);
105+
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
106+
return chibios_to_qmk(&status);
118107
}
119108

120-
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
121-
{
122-
i2c_address = devaddr;
123-
i2cStart(&I2C_DRIVER, &i2cconfig);
124-
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), &regaddr, 1, data, length, MS2ST(timeout));
125-
return chibios_to_qmk(&status);
109+
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
110+
i2c_address = devaddr;
111+
i2cStart(&I2C_DRIVER, &i2cconfig);
112+
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), &regaddr, 1, data, length, MS2ST(timeout));
113+
return chibios_to_qmk(&status);
126114
}
127115

128-
void i2c_stop(void)
129-
{
130-
i2cStop(&I2C_DRIVER);
131-
}
116+
void i2c_stop(void) { i2cStop(&I2C_DRIVER); }

‎drivers/arm/i2c_master.h

Lines changed: 45 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -27,84 +27,83 @@
2727
#include "ch.h"
2828
#include <hal.h>
2929

30-
3130
#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx)
32-
#define USE_I2CV1
31+
# define USE_I2CV1
3332
#endif
3433

3534
#ifdef I2C1_BANK
36-
#define I2C1_SCL_BANK I2C1_BANK
37-
#define I2C1_SDA_BANK I2C1_BANK
35+
# define I2C1_SCL_BANK I2C1_BANK
36+
# define I2C1_SDA_BANK I2C1_BANK
3837
#endif
3938

4039
#ifndef I2C1_SCL_BANK
41-
#define I2C1_SCL_BANK GPIOB
40+
# define I2C1_SCL_BANK GPIOB
4241
#endif
4342

4443
#ifndef I2C1_SDA_BANK
45-
#define I2C1_SDA_BANK GPIOB
44+
# define I2C1_SDA_BANK GPIOB
4645
#endif
4746

4847
#ifndef I2C1_SCL
49-
#define I2C1_SCL 6
48+
# define I2C1_SCL 6
5049
#endif
5150
#ifndef I2C1_SDA
52-
#define I2C1_SDA 7
51+
# define I2C1_SDA 7
5352
#endif
5453

5554
#ifdef USE_I2CV1
56-
#ifndef I2C1_OPMODE
57-
#define I2C1_OPMODE OPMODE_I2C
58-
#endif
59-
#ifndef I2C1_CLOCK_SPEED
60-
#define I2C1_CLOCK_SPEED 100000 /* 400000 */
61-
#endif
62-
#ifndef I2C1_DUTY_CYCLE
63-
#define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
64-
#endif
55+
# ifndef I2C1_OPMODE
56+
# define I2C1_OPMODE OPMODE_I2C
57+
# endif
58+
# ifndef I2C1_CLOCK_SPEED
59+
# define I2C1_CLOCK_SPEED 100000 /* 400000 */
60+
# endif
61+
# ifndef I2C1_DUTY_CYCLE
62+
# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
63+
# endif
6564
#else
66-
// The default PAL alternate modes are used to signal that the pins are used for I2C
67-
#ifndef I2C1_SCL_PAL_MODE
68-
#define I2C1_SCL_PAL_MODE 4
69-
#endif
70-
#ifndef I2C1_SDA_PAL_MODE
71-
#define I2C1_SDA_PAL_MODE 4
72-
#endif
65+
// The default PAL alternate modes are used to signal that the pins are used for I2C
66+
# ifndef I2C1_SCL_PAL_MODE
67+
# define I2C1_SCL_PAL_MODE 4
68+
# endif
69+
# ifndef I2C1_SDA_PAL_MODE
70+
# define I2C1_SDA_PAL_MODE 4
71+
# endif
7372

74-
// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
75-
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
76-
#ifndef I2C1_TIMINGR_PRESC
77-
#define I2C1_TIMINGR_PRESC 15U
78-
#endif
79-
#ifndef I2C1_TIMINGR_SCLDEL
80-
#define I2C1_TIMINGR_SCLDEL 4U
81-
#endif
82-
#ifndef I2C1_TIMINGR_SDADEL
83-
#define I2C1_TIMINGR_SDADEL 2U
84-
#endif
85-
#ifndef I2C1_TIMINGR_SCLH
86-
#define I2C1_TIMINGR_SCLH 15U
87-
#endif
88-
#ifndef I2C1_TIMINGR_SCLL
89-
#define I2C1_TIMINGR_SCLL 21U
90-
#endif
73+
// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
74+
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
75+
# ifndef I2C1_TIMINGR_PRESC
76+
# define I2C1_TIMINGR_PRESC 15U
77+
# endif
78+
# ifndef I2C1_TIMINGR_SCLDEL
79+
# define I2C1_TIMINGR_SCLDEL 4U
80+
# endif
81+
# ifndef I2C1_TIMINGR_SDADEL
82+
# define I2C1_TIMINGR_SDADEL 2U
83+
# endif
84+
# ifndef I2C1_TIMINGR_SCLH
85+
# define I2C1_TIMINGR_SCLH 15U
86+
# endif
87+
# ifndef I2C1_TIMINGR_SCLL
88+
# define I2C1_TIMINGR_SCLL 21U
89+
# endif
9190
#endif
9291

9392
#ifndef I2C_DRIVER
94-
#define I2C_DRIVER I2CD1
93+
# define I2C_DRIVER I2CD1
9594
#endif
9695

9796
typedef int16_t i2c_status_t;
9897

9998
#define I2C_STATUS_SUCCESS (0)
100-
#define I2C_STATUS_ERROR (-1)
99+
#define I2C_STATUS_ERROR (-1)
101100
#define I2C_STATUS_TIMEOUT (-2)
102101

103-
void i2c_init(void);
102+
void i2c_init(void);
104103
i2c_status_t i2c_start(uint8_t address);
105104
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
106105
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
107-
i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t * tx_body, uint16_t tx_length, uint8_t * rx_body, uint16_t rx_length);
106+
i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t* tx_body, uint16_t tx_length, uint8_t* rx_body, uint16_t rx_length);
108107
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
109108
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
110-
void i2c_stop(void);
109+
void i2c_stop(void);

‎drivers/avr/analog.c

Lines changed: 21 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -21,49 +21,38 @@
2121
#include <stdint.h>
2222
#include "analog.h"
2323

24+
static uint8_t aref = (1 << REFS0); // default to AREF = Vcc
2425

25-
static uint8_t aref = (1<<REFS0); // default to AREF = Vcc
26-
27-
28-
void analogReference(uint8_t mode)
29-
{
30-
aref = mode & 0xC0;
31-
}
32-
26+
void analogReference(uint8_t mode) { aref = mode & 0xC0; }
3327

3428
// Arduino compatible pin input
35-
int16_t analogRead(uint8_t pin)
36-
{
29+
int16_t analogRead(uint8_t pin) {
3730
#if defined(__AVR_ATmega32U4__)
38-
static const uint8_t PROGMEM pin_to_mux[] = {
39-
0x00, 0x01, 0x04, 0x05, 0x06, 0x07,
40-
0x25, 0x24, 0x23, 0x22, 0x21, 0x20};
41-
if (pin >= 12) return 0;
42-
return adc_read(pgm_read_byte(pin_to_mux + pin));
31+
static const uint8_t PROGMEM pin_to_mux[] = {0x00, 0x01, 0x04, 0x05, 0x06, 0x07, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20};
32+
if (pin >= 12) return 0;
33+
return adc_read(pgm_read_byte(pin_to_mux + pin));
4334
#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
44-
if (pin >= 8) return 0;
45-
return adc_read(pin);
35+
if (pin >= 8) return 0;
36+
return adc_read(pin);
4637
#else
47-
return 0;
38+
return 0;
4839
#endif
4940
}
5041

5142
// Mux input
52-
int16_t adc_read(uint8_t mux)
53-
{
43+
int16_t adc_read(uint8_t mux) {
5444
#if defined(__AVR_AT90USB162__)
55-
return 0;
45+
return 0;
5646
#else
57-
uint8_t low;
58-
59-
ADCSRA = (1<<ADEN) | ADC_PRESCALER; // enable ADC
60-
ADCSRB = (1<<ADHSM) | (mux & 0x20); // high speed mode
61-
ADMUX = aref | (mux & 0x1F); // configure mux input
62-
ADCSRA = (1<<ADEN) | ADC_PRESCALER | (1<<ADSC); // start the conversion
63-
while (ADCSRA & (1<<ADSC)) ; // wait for result
64-
low = ADCL; // must read LSB first
65-
return (ADCH << 8) | low; // must read MSB only once!
47+
uint8_t low;
48+
49+
ADCSRA = (1 << ADEN) | ADC_PRESCALER; // enable ADC
50+
ADCSRB = (1 << ADHSM) | (mux & 0x20); // high speed mode
51+
ADMUX = aref | (mux & 0x1F); // configure mux input
52+
ADCSRA = (1 << ADEN) | ADC_PRESCALER | (1 << ADSC); // start the conversion
53+
while (ADCSRA & (1 << ADSC))
54+
; // wait for result
55+
low = ADCL; // must read LSB first
56+
return (ADCH << 8) | low; // must read MSB only once!
6657
#endif
6758
}
68-
69-

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