Small overhaul of OpenCM3 code, rework Nucleo-L4R5ZI target a bit, and add CW308T-STM32F415 target (#259)

* Only compile the specific libopencm3 library needed

* Add experimental support for CW308T-STM32F415

* Shut up the linker errors

* Shut up unused parameter warning

* Fix Keccaktest bin generation

* Update libopencm3

* Adapt to renamed constants

* Compile the board test with fast and slow clock

* Use wrapped symbols instead of overriding

* Overhaul clocking for L4R5ZI board

Author: rpls

common/hal-opencm3.c

@@ -56,6 +56,17 @@ const struct rcc_clock_scale benchmarkclock = {
 #include <libopencm3/stm32/usart.h>
 #include <libopencm3/stm32/flash.h>
 
+#define SERIAL_GPIO GPIOA
+#define SERIAL_USART USART1
+#define SERIAL_PINS (GPIO9 | GPIO10)
+#define STM32
+#define CW_BOARD
+#elif defined(STM32F415RGT6)
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/flash.h>
+
 #define SERIAL_GPIO GPIOA
 #define SERIAL_USART USART1
 #define SERIAL_PINS (GPIO9 | GPIO10)
@@ -119,6 +130,7 @@ static void clock_setup(enum clock_mode clock)
 
   flash_prefetch_enable();
 #elif defined(CW_BOARD)
+  (void) clock;
   /* Some STM32 Platform */
   rcc_periph_clock_enable(RCC_GPIOH);
   rcc_osc_off(RCC_HSE);
@@ -131,8 +143,13 @@ static void clock_setup(enum clock_mode clock)
   rcc_apb2_frequency = 7372800;
   _clock_freq = 7372800;
   rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE);
+#if defined(STM32F3)
   rcc_set_ppre1(RCC_CFGR_PPRE1_DIV_NONE);
   rcc_set_ppre2(RCC_CFGR_PPRE2_DIV_NONE);
+#elif defined(STM32F4)
+  rcc_set_ppre1(RCC_CFGR_PPRE_DIV_NONE);
+  rcc_set_ppre2(RCC_CFGR_PPRE_DIV_NONE);
+#endif
   rcc_set_sysclk_source(RCC_CFGR_SW_HSE);
   rcc_wait_for_sysclk_status(RCC_HSE);
 #elif defined(NUCLEO_BOARD)
@@ -147,8 +164,8 @@ static void clock_setup(enum clock_mode clock)
     rcc_apb2_frequency = 16000000;
     _clock_freq = 16000000;
     rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
-    rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
-    rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
+    rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
+    rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
     flash_dcache_enable();
     flash_icache_enable();
     flash_set_ws(FLASH_ACR_LATENCY_0WS);
@@ -165,8 +182,8 @@ static void clock_setup(enum clock_mode clock)
     rcc_apb2_frequency = 80000000;
     _clock_freq = 80000000;
     rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
-    rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
-    rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
+    rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
+    rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
     rcc_osc_off(RCC_PLL);
     while(rcc_is_osc_ready(RCC_PLL));
     /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 80MHz). */
@@ -189,24 +206,33 @@ static void clock_setup(enum clock_mode clock)
   rcc_periph_clock_enable(RCC_PWR);
   rcc_periph_clock_enable(RCC_SYSCFG);
   pwr_set_vos_scale(PWR_SCALE1);
+  /* The L4R5ZI chip also needs the R1MODE bit in PWR_CR5 register set, but
+     OpenCM3 doesn't support this yet. But luckily the default value for the bit
+     is 1. */
   switch (clock) {
   case CLOCK_BENCHMARK:
     /* Benchmark straight from the HSI16 without prescaling */
     rcc_osc_on(RCC_HSI16);
     rcc_wait_for_osc_ready(RCC_HSI16);
-    rcc_ahb_frequency = 16000000;
-    rcc_apb1_frequency = 16000000;
-    rcc_apb2_frequency = 16000000;
-    _clock_freq = 16000000;
+    rcc_ahb_frequency = 20000000;
+    rcc_apb1_frequency = 20000000;
+    rcc_apb2_frequency = 20000000;
+    _clock_freq = 20000000;
     rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
-    rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
-    rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
+    rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
+    rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
+    rcc_osc_off(RCC_PLL);
+    while(rcc_is_osc_ready(RCC_PLL));
+    /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 20MHz). */
+    _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 10, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV8);
+    /* Enable PLL oscillator and wait for it to stabilize. */
+    rcc_osc_on(RCC_PLL);
     flash_dcache_enable();
     flash_icache_enable();
     flash_set_ws(FLASH_ACR_LATENCY_0WS);
     flash_prefetch_enable();
-    rcc_set_sysclk_source(RCC_CFGR_SW_HSI16);
-    rcc_wait_for_sysclk_status(RCC_HSI16);
+    rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
+    rcc_wait_for_sysclk_status(RCC_PLL);
     break;
   case CLOCK_FAST:
   default:
@@ -217,12 +243,12 @@ static void clock_setup(enum clock_mode clock)
     rcc_apb2_frequency = 120000000;
     _clock_freq = 120000000;
     rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
-    rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
-    rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
+    rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
+    rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
     rcc_osc_off(RCC_PLL);
     while(rcc_is_osc_ready(RCC_PLL));
     /* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 120MHz). */
-    _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 2, 30, 2u, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV2);
+    _rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 15, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV2);
     /* Enable PLL oscillator and wait for it to stabilize. */
     rcc_osc_on(RCC_PLL);
     rcc_wait_for_osc_ready(RCC_PLL);
@@ -235,7 +261,9 @@ static void clock_setup(enum clock_mode clock)
     break;
   }
   rcc_osc_on(RCC_HSI48); /* HSI48 must always be on for RNG */
+  rcc_wait_for_osc_ready(RCC_HSI48);
   rcc_periph_clock_enable(RCC_RNG);
+  rcc_set_clock48_source(RCC_CCIPR_CLK48SEL_HSI48);
   rng_enable();
 #else
 #error Unsupported platform
@@ -358,3 +386,74 @@ size_t hal_get_stack_size(void)
 	__asm__ volatile ("mov %0, sp" : "=r" (cur_stack));
   return cur_stack - heap_end;
 }
+
+/* Implement some system calls to shut up the linker warnings */
+
+#include <errno.h>
+#undef errno
+extern int errno;
+
+int __wrap__close(int fd)
+{
+  errno = ENOSYS;
+	(void) fd;
+	return -1;
+}
+
+#include <sys/stat.h>
+
+int __wrap__fstat(int fd, struct stat* buf)
+{
+  (void) fd;
+  (void) buf;
+  errno = ENOSYS;
+	return -1;
+}
+
+int __wrap__getpid(void)
+{
+  errno = ENOSYS;
+	return -1;
+}
+
+int __wrap__isatty(int file)
+{
+  (void) file;
+  errno = ENOSYS;
+  return 0;
+}
+
+int __wrap__kill(int pid, int sig)
+{
+  (void) pid;
+  (void) sig;
+  errno = ENOSYS;
+	return -1;
+}
+
+int __wrap__lseek(int fd, int ptr, int dir)
+{
+  (void) fd;
+  (void) ptr;
+  (void) dir;
+  errno = ENOSYS;
+	return -1;
+}
+
+int __wrap__read(int fd, char* ptr, int len)
+{
+  (void) fd;
+  (void) ptr;
+  (void) len;
+  errno = ENOSYS;
+	return -1;
+}
+
+int __wrap__write(int fd, const char* ptr, int len)
+{
+  (void) fd;
+  (void) ptr;
+  (void) len;
+  errno = ENOSYS;
+	return -1;
+}

common/test.c

@@ -124,9 +124,13 @@ static void memory_timing_test(void)
 }
 #endif
 
+#ifndef CLOCK_TEST
+#define CLOCK_TEST CLOCK_BENCHMARK
+#endif
+
 int main(void)
 {
-  hal_setup(CLOCK_FAST);
+  hal_setup(CLOCK_TEST);
   hal_send_str("Hello world");
   send_unsigned("Stack Size", hal_get_stack_size());
   unsigned rnd;

common/testfast.c

@@ -0,0 +1 @@
+test.c

interface.py

@@ -10,7 +10,7 @@ def parse_arguments():
         "-p",
         "--platform",
         help="The PQM4 platform",
-        choices=["stm32f4discovery", "nucleo-l476rg", "nucleo-l4r5zi", "cw308t-stm32f3", "mps2-an386"],
+        choices=["stm32f4discovery", "nucleo-l476rg", "nucleo-l4r5zi", "cw308t-stm32f3", "cw308t-stm32f415", "mps2-an386"],
         default="stm32f4discovery",
     )
     parser.add_argument(
@@ -39,7 +39,7 @@ def get_platform(args):
     elif args.platform == "nucleo-l4r5zi":
         bin_type = 'hex'
         platform = platforms.OpenOCD("st_nucleo_l4r5.cfg", args.uart)
-    elif args.platform == "cw308t-stm32f3":
+    elif args.platform in ["cw308t-stm32f3", "cw308t-stm32f415"]:
         bin_type = 'hex'
         platform = platforms.ChipWhisperer()
     elif args.platform == 'mps2-an386':

libopencm3

@@ -1,4 +1,5 @@
 DEVICE=stm32f303rct7
+OPENCM3_TARGET=lib/stm32/f3
 
 EXCLUDED_SCHEMES = \
 	mupq/pqclean/crypto_sign/sphincs-haraka-256f% \

mk/cw308t-stm32f3.mk

@@ -0,0 +1,14 @@
+DEVICE=stm32f415rgt6
+OPENCM3_TARGET=lib/stm32/f4
+
+EXCLUDED_SCHEMES = \
+	mupq/pqclean/crypto_sign/sphincs-haraka-256f% \
+	mupq/pqclean/crypto_sign/sphincs-shake256-256f% \
+	mupq/pqclean/crypto_sign/sphincs-sha256-256f% \
+	mupq/pqclean/crypto_kem/mceliece% \
+	mupq/crypto_sign/falcon-1024% \
+	mupq/crypto_sign/falcon-512% \
+	crypto_sign/falcon-1024% \
+	crypto_sign/falcon-512%
+
+include mk/opencm3.mk

mk/cw308t-stm32f415.mk

@@ -1,4 +1,5 @@
 DEVICE=stm32l476rg
+OPENCM3_TARGET=lib/stm32/l4
 
 EXCLUDED_SCHEMES = \
 	mupq/pqclean/crypto_kem/mceliece% \

mk/nucleo-l476rg.mk

@@ -1,4 +1,5 @@
 DEVICE=stm32l4r5zi
+OPENCM3_TARGET=lib/stm32/l4
 
 EXCLUDED_SCHEMES = \
 	mupq/pqclean/crypto_kem/mceliece% \
@@ -9,4 +10,7 @@ DEVICES_DATA := ldscripts/devices.data
 elf/boardtest.elf: CPPFLAGS+=-DSRAM_TIMING_TEST -DHAS_SRAM2 -DHAS_SRAM3
 elf/boardtest.elf: LDSCRIPT=ldscripts/$(PLATFORM)-ramtest.ld
 
+elf/boardtest-fast.elf: CPPFLAGS+=-DSRAM_TIMING_TEST -DHAS_SRAM2 -DHAS_SRAM3
+elf/boardtest-fast.elf: LDSCRIPT=ldscripts/$(PLATFORM)-ramtest.ld
+
 include mk/opencm3.mk

mk/nucleo-l4r5zi.mk

@@ -61,7 +61,7 @@ LDFLAGS += -L$(OPENCM3_DIR)/lib
 CPPFLAGS += -I$(OPENCM3_DIR)/include
 
 $(OPENCM3_DIR)/lib/lib$(LIBNAME).a:
-	$(MAKE) -C $(OPENCM3_DIR)
+	$(MAKE) -C $(OPENCM3_DIR) $(OPENCM3_TARGET)
 
 obj/common/hal-opencm3.c.o: $(OPENCM3_DIR)/lib/lib$(LIBNAME).a
 
@@ -89,6 +89,14 @@ CFLAGS += \
 LDFLAGS += \
 	--specs=nosys.specs \
 	-Wl,--wrap=_sbrk \
+	-Wl,--wrap=_close \
+	-Wl,--wrap=_isatty \
+	-Wl,--wrap=_kill \
+	-Wl,--wrap=_lseek \
+	-Wl,--wrap=_read \
+	-Wl,--wrap=_write \
+	-Wl,--wrap=_fstat \
+	-Wl,--wrap=_getpid \
 	-nostartfiles \
 	-ffreestanding \
 	-T$(LDSCRIPT) \

mk/opencm3.mk

@@ -1,4 +1,5 @@
 DEVICE=stm32f407vg
+OPENCM3_TARGET=lib/stm32/f4
 
 EXCLUDED_SCHEMES = \
 	mupq/pqclean/crypto_kem/mceliece% \
@@ -7,6 +8,7 @@ EXCLUDED_SCHEMES = \
 include mk/opencm3.mk
 
 elf/boardtest.elf: CPPFLAGS+=-DSRAM_TIMING_TEST -DHAS_SRAM2 -DHAS_CCM
+elf/boardtest-fast.elf: CPPFLAGS+=-DSRAM_TIMING_TEST -DHAS_SRAM2 -DHAS_CCM
 
 elf/crypto_kem_frodokem640aes_m4_%.elf: LDSCRIPT=ldscripts/stm32f4discovery_fullram.ld
 elf/mupq_pqclean_crypto_kem_frodokem640shake_opt_%.elf: LDSCRIPT=ldscripts/stm32f4discovery_fullram.ld

mk/stm32f4discovery.mk

@@ -2,6 +2,11 @@ ifeq ($(AIO),1)
 elf/boardtest.elf: common/test.c $(LINKDEPS) $(CONFIG)
 	$(compiletest)
 
+elf/boardtest-fast.elf: common/testfast.c $(LINKDEPS) $(CONFIG)
+	$(compiletest)
+
+elf/boardtest-fast.elf: CPPFLAGS += -DCLOCK_TEST=CLOCK_FAST
+
 elf/aestest.elf: common/aestest.c $(LINKDEPS) $(CONFIG)
 	$(compiletest)
 
@@ -10,10 +15,14 @@ elf/keccaktest.elf: common/keccaktest.c $(LINKDEPS) $(CONFIG)
 else
 elf/boardtest.elf: $(call objs,common/test.c) $(LINKDEPS) $(CONFIG)
 
+elf/boardtest-fast.elf: $(call objs,common/testfast.c) $(LINKDEPS) $(CONFIG)
+
+$(call objs,common/testfast.c): CPPFLAGS += -DCLOCK_TEST=CLOCK_FAST
+
 elf/aestest.elf: $(call objs,common/aestest.c) $(LINKDEPS) $(CONFIG)
 
 elf/keccaktest.elf: $(call objs,common/keccaktest.c) $(LINKDEPS) $(CONFIG)
 endif
 
 tests: elf/boardtest.elf elf/aestest.elf elf/keccaktest.elf
-tests-bin: bin/boardtest.bin bin/aestest.bin bin/keccaktest.elf
+tests-bin: bin/boardtest.bin bin/aestest.bin bin/keccaktest.bin