stabilize and de-randomize verilog output

[jordens]

m-labs/artiq#341

[mithro]

Hrm, I thought we had fixed most of this - see m-labs/misoc#20

[jordens]

Nope.

[sbourdeauducq]

Fixed the non-determinism in the ARTIQ Pipistrello gateware.

[mithro]

@sbourdeauducq How did you test for non-determinism in the ARTIQ Pipistrello gateware?

[sbourdeauducq]

#TARGET=misoc.targets.pipistrello
TARGET=artiq.gateware.targets.pipistrello

python -m $TARGET --no-compile-software --no-compile-gateware --output-dir nd1
python -m $TARGET --no-compile-software --no-compile-gateware --output-dir nd2
diff -Nau nd1/gateware/top.v nd2/gateware/top.v

and run in a loop.

[mithro]

You might want to also check with something like this;

TARGET=artiq.gateware.targets.pipistrello

PYTHONHASHSEED=1 python -m $TARGET --no-compile-software --no-compile-gateware --output-dir nd1
PYTHONHASHSEED=2 python -m $TARGET --no-compile-software --no-compile-gateware --output-dir nd2
diff -Nau nd1/gateware/top.v nd2/gateware/top.v