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- ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool build-release/bin/opt --version 5
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- ; RUN: opt < %s -S -passes="msan<eager-checks;track-origins=2>" -msan-instrumentation-with-call-threshold=0 -disable-verify | FileCheck %s
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- ;
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- ; UNSUPPORTED: target={{.*}}
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+ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool build/bin/opt --version 5
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+ ; RUN: opt < %s -S -passes="msan<eager-checks;track-origins=2>" -msan-instrumentation-with-call-threshold=0 | FileCheck %s
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;
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; This test illustrates a bug in MemorySanitizer that will shortly be fixed
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; (https://github.com/llvm/llvm-project/pull/96722).
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;
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; '-msan-instrumentation-with-call-threshold=0' makes it possible to detect the
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; bug with a short test case.
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- ;
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- ; '-disable-verify' with a release build is needed to avoid a compiler crash
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- ; (e.g., to autogenerate the assertions).
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- ;
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
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target triple = "aarch64-grtev4-linux-gnu"
@@ -28,36 +22,31 @@ define dso_local void @_Z1cv() local_unnamed_addr #0 {
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi <4 x i16> [ [[_MSLD]], %[[ENTRY]] ], [ [[_MSLD3:%.*]], %[[FOR_COND]] ]
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- ; CHECK-NEXT: [[_MSPHI_O:%.*]] = phi i32 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP15 :%.*]], %[[FOR_COND]] ]
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+ ; CHECK-NEXT: [[_MSPHI_O:%.*]] = phi i32 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP11 :%.*]], %[[FOR_COND]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = phi <4 x i16> [ [[DOTPRE]], %[[ENTRY]] ], [ [[TMP5:%.*]], %[[FOR_COND]] ]
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; CHECK-NEXT: [[_MSPHI_S1:%.*]] = phi <4 x i16> [ <i16 -1, i16 -1, i16 -1, i16 -1>, %[[ENTRY]] ], [ [[_MSLD3]], %[[FOR_COND]] ]
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- ; CHECK-NEXT: [[_MSPHI_O2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP15 ]], %[[FOR_COND]] ]
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+ ; CHECK-NEXT: [[_MSPHI_O2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP11 ]], %[[FOR_COND]] ]
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; CHECK-NEXT: [[E_0:%.*]] = phi <4 x i16> [ undef, %[[ENTRY]] ], [ [[TMP5]], %[[FOR_COND]] ]
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; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSPHI_S1]], <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[E_0]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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- ;
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- ; Editor's note: the following zext instructions are invalid
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- ; ('zext source and destination must both be a vector or neither')
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- ;
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- ; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[_MSPHI_S]] to i64
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+ ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[_MSPHI_S]] to i64
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; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP2]], i32 zeroext [[_MSPHI_O]])
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- ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[_MSPROP]] to i64
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- ;
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+ ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i64
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; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP3]], i32 zeroext [[_MSPHI_O2]])
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; CHECK-NEXT: [[CALL:%.*]] = tail call noundef i32 @_Z1b11__Int16x4_tS_(<4 x i16> noundef [[TMP1]], <4 x i16> noundef [[LANE]])
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; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
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- ; CHECK-NEXT: [[TMP8 :%.*]] = inttoptr i64 [[CONV]] to ptr
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- ; CHECK-NEXT: [[TMP5]] = load <4 x i16>, ptr [[TMP8 ]], align 8, !tbaa [[TBAA0]]
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- ; CHECK-NEXT: [[TMP10 :%.*]] = ptrtoint ptr [[TMP8 ]] to i64
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- ; CHECK-NEXT: [[TMP11 :%.*]] = xor i64 [[TMP10 ]], 193514046488576
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- ; CHECK-NEXT: [[TMP12 :%.*]] = inttoptr i64 [[TMP11 ]] to ptr
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- ; CHECK-NEXT: [[TMP13 :%.*]] = add i64 [[TMP11 ]], 35184372088832
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- ; CHECK-NEXT: [[TMP14 :%.*]] = inttoptr i64 [[TMP13 ]] to ptr
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- ; CHECK-NEXT: [[_MSLD3]] = load <4 x i16>, ptr [[TMP12 ]], align 8
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- ; CHECK-NEXT: [[TMP15 ]] = load i32, ptr [[TMP14 ]], align 8
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+ ; CHECK-NEXT: [[TMP4 :%.*]] = inttoptr i64 [[CONV]] to ptr
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+ ; CHECK-NEXT: [[TMP5]] = load <4 x i16>, ptr [[TMP4 ]], align 8, !tbaa [[TBAA0]]
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+ ; CHECK-NEXT: [[TMP6 :%.*]] = ptrtoint ptr [[TMP4 ]] to i64
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+ ; CHECK-NEXT: [[TMP7 :%.*]] = xor i64 [[TMP6 ]], 193514046488576
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+ ; CHECK-NEXT: [[TMP8 :%.*]] = inttoptr i64 [[TMP7 ]] to ptr
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+ ; CHECK-NEXT: [[TMP9 :%.*]] = add i64 [[TMP7 ]], 35184372088832
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+ ; CHECK-NEXT: [[TMP10 :%.*]] = inttoptr i64 [[TMP9 ]] to ptr
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+ ; CHECK-NEXT: [[_MSLD3]] = load <4 x i16>, ptr [[TMP8 ]], align 8
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+ ; CHECK-NEXT: [[TMP11 ]] = load i32, ptr [[TMP10 ]], align 8
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; CHECK-NEXT: store <4 x i16> [[_MSLD3]], ptr inttoptr (i64 xor (i64 ptrtoint (ptr @_Z1cv to i64), i64 193514046488576) to ptr), align 8
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- ; CHECK-NEXT: [[TMP16 :%.*]] = bitcast <4 x i16> [[_MSLD3]] to i64
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- ; CHECK-NEXT: call void @__msan_maybe_store_origin_8(i64 zeroext [[TMP16 ]], ptr @_Z1cv, i32 zeroext [[TMP15 ]])
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+ ; CHECK-NEXT: [[TMP12 :%.*]] = bitcast <4 x i16> [[_MSLD3]] to i64
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+ ; CHECK-NEXT: call void @__msan_maybe_store_origin_8(i64 zeroext [[TMP12 ]], ptr @_Z1cv, i32 zeroext [[TMP11 ]])
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; CHECK-NEXT: store <4 x i16> [[TMP5]], ptr @_Z1cv, align 8, !tbaa [[TBAA0]]
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; CHECK-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
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;
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