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[RISCV] Add Andes A25/AX25 processor definition (#140681)
Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable CPUs that implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for A25/AX25: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25/ Scheduling model will be implemented in a later PR.
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‎clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c

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// RUN: %clang --target=riscv32 -mcpu=andes-a25 --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c

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// RUN: %clang --target=riscv64 -mcpu=andes-ax25 --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/riscv-cpus.c

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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
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// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s
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// MCPU-ANDES-A25: "-target-cpu" "andes-a25"
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-a25.c`
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// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s
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// MTUNE-ANDES-A25: "-tune-cpu" "andes-a25"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s
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// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25"
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax25.c`
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// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s
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// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
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// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
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// RISCV32-NEXT: note: valid target CPU values are:
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// RISCV32-SAME: {{^}} andes-a45
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// RISCV32-SAME: {{^}} andes-a25
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// RISCV32-SAME: {{^}}, andes-a45
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// RISCV32-SAME: {{^}}, andes-n45
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// RISCV32-SAME: {{^}}, generic-rv32
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// RISCV32-SAME: {{^}}, rocket-rv32
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are:
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// RISCV64-SAME: {{^}} andes-ax45
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// RISCV64-SAME: {{^}} andes-ax25
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// RISCV64-SAME: {{^}}, andes-ax45
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// RISCV64-SAME: {{^}}, andes-nx45
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// RISCV64-SAME: {{^}}, generic-rv64
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// RISCV64-SAME: {{^}}, mips-p8700
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are:
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// TUNE-RISCV32-SAME: {{^}} andes-a45
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// TUNE-RISCV32-SAME: {{^}} andes-a25
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// TUNE-RISCV32-SAME: {{^}}, andes-a45
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// TUNE-RISCV32-SAME: {{^}}, andes-n45
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// TUNE-RISCV32-SAME: {{^}}, generic-rv32
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// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are:
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// TUNE-RISCV64-SAME: {{^}} andes-ax45
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// TUNE-RISCV64-SAME: {{^}} andes-ax25
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// TUNE-RISCV64-SAME: {{^}}, andes-ax45
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// TUNE-RISCV64-SAME: {{^}}, andes-nx45
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// TUNE-RISCV64-SAME: {{^}}, generic-rv64
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// TUNE-RISCV64-SAME: {{^}}, mips-p8700

‎llvm/docs/ReleaseNotes.md

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extension.
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* Adds experimental assembler support for the SiFive Xsfmm* Attached Matrix
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Extensions.
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* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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FeatureStdExtZcb,
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FeatureStdExtZcmp]>;
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def ANDES_A25 : RISCVProcessorModel<"andes-a25",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtB,
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FeatureStdExtZbc,
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FeatureVendorXAndesPerf]>;
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def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtB,
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FeatureStdExtZbc,
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FeatureVendorXAndesPerf]>;
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def ANDES_N45 : RISCVProcessorModel<"andes-n45",
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NoSchedModel,
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[Feature32Bit,

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