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[X86] Remove extra MOV after widening atomic load
This change adds patterns to optimize out an extra MOV present after widening the atomic load. commit-id:45989503
1 parent 0b8a020 commit 4383732

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2 files changed

+30
-20
lines changed

2 files changed

+30
-20
lines changed

llvm/lib/Target/X86/X86InstrCompiler.td

+7
Original file line numberDiff line numberDiff line change
@@ -1200,6 +1200,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>;
12001200
def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>;
12011201
def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>;
12021202

1203+
def : Pat<(v4i32 (scalar_to_vector (i32 (anyext (i16 (atomic_load_16 addr:$src)))))),
1204+
(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i8>
1205+
def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32 addr:$src)))),
1206+
(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i16>
1207+
def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src)))),
1208+
(MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float>
1209+
12031210
// Floating point loads/stores.
12041211
def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),
12051212
(MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>;

llvm/test/CodeGen/X86/atomic-load-store.ll

+23-20
Original file line numberDiff line numberDiff line change
@@ -149,8 +149,7 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {
149149
define <2 x i8> @atomic_vec2_i8(ptr %x) {
150150
; CHECK3-LABEL: atomic_vec2_i8:
151151
; CHECK3: ## %bb.0:
152-
; CHECK3-NEXT: movzwl (%rdi), %eax
153-
; CHECK3-NEXT: movd %eax, %xmm0
152+
; CHECK3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
154153
; CHECK3-NEXT: retq
155154
;
156155
; CHECK0-LABEL: atomic_vec2_i8:
@@ -165,20 +164,23 @@ define <2 x i8> @atomic_vec2_i8(ptr %x) {
165164
}
166165

167166
define <2 x i16> @atomic_vec2_i16(ptr %x) {
168-
; CHECK-LABEL: atomic_vec2_i16:
169-
; CHECK: ## %bb.0:
170-
; CHECK-NEXT: movl (%rdi), %eax
171-
; CHECK-NEXT: movd %eax, %xmm0
172-
; CHECK-NEXT: retq
167+
; CHECK3-LABEL: atomic_vec2_i16:
168+
; CHECK3: ## %bb.0:
169+
; CHECK3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
170+
; CHECK3-NEXT: retq
171+
;
172+
; CHECK0-LABEL: atomic_vec2_i16:
173+
; CHECK0: ## %bb.0:
174+
; CHECK0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
175+
; CHECK0-NEXT: retq
173176
%ret = load atomic <2 x i16>, ptr %x acquire, align 4
174177
ret <2 x i16> %ret
175178
}
176179

177180
define <2 x ptr addrspace(270)> @atomic_vec2_ptr270(ptr %x) {
178181
; CHECK-LABEL: atomic_vec2_ptr270:
179182
; CHECK: ## %bb.0:
180-
; CHECK-NEXT: movq (%rdi), %rax
181-
; CHECK-NEXT: movq %rax, %xmm0
183+
; CHECK-NEXT: movq (%rdi), %xmm0
182184
; CHECK-NEXT: retq
183185
%ret = load atomic <2 x ptr addrspace(270)>, ptr %x acquire, align 8
184186
ret <2 x ptr addrspace(270)> %ret
@@ -187,8 +189,7 @@ define <2 x ptr addrspace(270)> @atomic_vec2_ptr270(ptr %x) {
187189
define <2 x i32> @atomic_vec2_i32_align(ptr %x) {
188190
; CHECK-LABEL: atomic_vec2_i32_align:
189191
; CHECK: ## %bb.0:
190-
; CHECK-NEXT: movq (%rdi), %rax
191-
; CHECK-NEXT: movq %rax, %xmm0
192+
; CHECK-NEXT: movq (%rdi), %xmm0
192193
; CHECK-NEXT: retq
193194
%ret = load atomic <2 x i32>, ptr %x acquire, align 8
194195
ret <2 x i32> %ret
@@ -197,8 +198,7 @@ define <2 x i32> @atomic_vec2_i32_align(ptr %x) {
197198
define <2 x float> @atomic_vec2_float_align(ptr %x) {
198199
; CHECK-LABEL: atomic_vec2_float_align:
199200
; CHECK: ## %bb.0:
200-
; CHECK-NEXT: movq (%rdi), %rax
201-
; CHECK-NEXT: movq %rax, %xmm0
201+
; CHECK-NEXT: movq (%rdi), %xmm0
202202
; CHECK-NEXT: retq
203203
%ret = load atomic <2 x float>, ptr %x acquire, align 8
204204
ret <2 x float> %ret
@@ -354,20 +354,23 @@ define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
354354
}
355355

356356
define <4 x i8> @atomic_vec4_i8(ptr %x) nounwind {
357-
; CHECK-LABEL: atomic_vec4_i8:
358-
; CHECK: ## %bb.0:
359-
; CHECK-NEXT: movl (%rdi), %eax
360-
; CHECK-NEXT: movd %eax, %xmm0
361-
; CHECK-NEXT: retq
357+
; CHECK3-LABEL: atomic_vec4_i8:
358+
; CHECK3: ## %bb.0:
359+
; CHECK3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
360+
; CHECK3-NEXT: retq
361+
;
362+
; CHECK0-LABEL: atomic_vec4_i8:
363+
; CHECK0: ## %bb.0:
364+
; CHECK0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
365+
; CHECK0-NEXT: retq
362366
%ret = load atomic <4 x i8>, ptr %x acquire, align 4
363367
ret <4 x i8> %ret
364368
}
365369

366370
define <4 x i16> @atomic_vec4_i16(ptr %x) nounwind {
367371
; CHECK-LABEL: atomic_vec4_i16:
368372
; CHECK: ## %bb.0:
369-
; CHECK-NEXT: movq (%rdi), %rax
370-
; CHECK-NEXT: movq %rax, %xmm0
373+
; CHECK-NEXT: movq (%rdi), %xmm0
371374
; CHECK-NEXT: retq
372375
%ret = load atomic <4 x i16>, ptr %x acquire, align 8
373376
ret <4 x i16> %ret

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