@@ -297,7 +297,7 @@ def FormalOp : VerifOp<"formal", [
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into the hardware to be tested. Testing tools will then try to find concrete
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values for them that violate any asserts or make any covers true.
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- ### Example
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+ #### Example
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```
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verif.formal @AdderTest {myParam = 42, myTag = "hello"} {
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%0 = verif.symbolic_value : i42
@@ -309,7 +309,7 @@ def FormalOp : VerifOp<"formal", [
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}
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```
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- ### Parameters
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+ #### Parameters
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The following parameters have a predefined meaning and are interpreted by
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tools such as `circt-test` to guide execution of tests:
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@@ -362,15 +362,15 @@ def SimulationOp : VerifOp<"simulation", [
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by various tools. To describe a test, the body of this op should contain the
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hardware to be tested, alongside any necessary forms of stimulus generation.
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- ### Inputs
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+ #### Inputs
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The body has two block arguments as input values: a "clock" signal of type
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`!seq.clock` and an "init" signal of type `i1`. The clock signal starts at 0
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and continuously toggles between 0 and 1 throughout the simulation. The init
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signal starts at 1, remains 1 during a single 0-to-1 transition of the
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clock, and then drops to 0 for the remainder of the simulation.
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- ### Outputs
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+ #### Outputs
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The body must have a `verif.yield` terminator op with exactly two operands:
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@@ -384,7 +384,7 @@ def SimulationOp : VerifOp<"simulation", [
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time as the done signal. Simulators must signal failure to the operating
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system through a non-zero exit code.
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- ### Schedule
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+ #### Schedule
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The clock and init values adhere to the following schedule during
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simulation:
@@ -402,7 +402,7 @@ def SimulationOp : VerifOp<"simulation", [
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Simulation termination occurs when the done signal is 1 during a 0-to-1
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transition of the clock.
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- ### Example
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+ #### Example
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```
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verif.simulation @AdderTest {myParam = 42, myTag = "hello"} {
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^bb0(%clock: !seq.clock, %init: i1):
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