[SV] Add preprocessor include op (#8329)

Author: rwy7

include/circt/Dialect/SV/SVStatements.td

@@ -913,6 +913,22 @@ def MacroDefOp : SVOp<"macro.def",
   }];
 }
 
+def IncludeStyle
+    : I32EnumAttr<
+          "IncludeStyle",
+          "Double-quoted local include, or angle bracketed system include",
+          [I32EnumAttrCase<"Local", 0, "local">,
+           I32EnumAttrCase<"System", 1, "system">]> {
+  let genSpecializedAttr = 0;
+}
+
+def IncludeStyleAttr : EnumAttr<SVDialect, IncludeStyle, "include_style">;
+
+def IncludeOp : SVOp<"include"> {
+  let summary = "preprocessor `include directive";
+  let arguments = (ins IncludeStyleAttr:$style, StrAttr:$target);
+  let assemblyFormat = [{ $style $target attr-dict }];
+}
 
 //===----------------------------------------------------------------------===//
 // Function/Call

include/circt/Dialect/SV/SVVisitors.h

@@ -40,7 +40,7 @@ class Visitor {
             // Other Statements.
             AssignOp, BPAssignOp, PAssignOp, ForceOp, ReleaseOp, AliasOp,
             FWriteOp, SystemFunctionOp, VerbatimOp, MacroRefOp, FuncCallOp,
-            FuncCallProceduralOp, ReturnOp,
+            FuncCallProceduralOp, ReturnOp, IncludeOp,
             // Type declarations.
             InterfaceOp, InterfaceSignalOp, InterfaceModportOp,
             InterfaceInstanceOp, GetModportOp, AssignInterfaceSignalOp,
@@ -137,6 +137,7 @@ class Visitor {
   HANDLE(ReturnOp, Unhandled);
   HANDLE(VerbatimOp, Unhandled);
   HANDLE(MacroRefOp, Unhandled);
+  HANDLE(IncludeOp, Unhandled);
 
   // Type declarations.
   HANDLE(InterfaceOp, Unhandled);

lib/Conversion/ExportVerilog/ExportVerilog.cpp

@@ -4062,6 +4062,7 @@ class StmtEmitter : public EmitterBase,
   LogicalResult visitSV(FuncCallProceduralOp op);
   LogicalResult visitSV(FuncCallOp op);
   LogicalResult visitSV(ReturnOp op);
+  LogicalResult visitSV(IncludeOp op);
 
 public:
   ModuleEmitter &emitter;
@@ -4451,6 +4452,20 @@ LogicalResult StmtEmitter::visitSV(ReturnOp op) {
   return emitOutputLikeOp(op, ports);
 }
 
+LogicalResult StmtEmitter::visitSV(IncludeOp op) {
+  startStatement();
+  ps << "`include" << PP::nbsp;
+
+  if (op.getStyle() == IncludeStyle::System)
+    ps << "<" << op.getTarget() << ">";
+  else
+    ps << "\"" << op.getTarget() << "\"";
+
+  emitLocationInfo(op.getLoc());
+  setPendingNewline();
+  return success();
+}
+
 LogicalResult StmtEmitter::visitSV(FuncDPIImportOp importOp) {
   startStatement();
 
@@ -6713,7 +6728,7 @@ void SharedEmitterState::gatherFiles(bool separateModules) {
           collectPorts(op);
           // External modules are _not_ emitted.
         })
-        .Case<VerbatimOp, IfDefOp, MacroDefOp, FuncDPIImportOp>(
+        .Case<VerbatimOp, IfDefOp, MacroDefOp, IncludeOp, FuncDPIImportOp>(
             [&](Operation *op) {
               // Emit into a separate file using the specified file name or
               // replicate the operation in each outputfile.
@@ -6857,6 +6872,7 @@ static void emitOperation(VerilogEmitterState &state, Operation *op) {
       .Case<MacroDefOp, FuncDPIImportOp>(
           [&](auto op) { ModuleEmitter(state).emitStatement(op); })
       .Case<FuncOp>([&](auto op) { ModuleEmitter(state).emitFunc(op); })
+      .Case<IncludeOp>([&](auto op) { ModuleEmitter(state).emitStatement(op); })
       .Default([&](auto *op) {
         state.encounteredError = true;
         op->emitError("unknown operation (ExportVerilog::emitOperation)");

test/Conversion/ExportVerilog/verilog-basic.mlir

@@ -801,3 +801,9 @@ sv.bind #hw.innerNameRef<@SiFive_MulDiv::@__ETC_SiFive_MulDiv_assert>
 // CHECK-NEXT:  ._io_req_ready_output (1'h0)
 // CHECK-NEXT:  .resetSignalName      (reset),
 // CHECK-NEXT:  .clock                (clock)
+
+// CHECK: `include "foo/bar"
+sv.include local "foo/bar"
+
+// CHECK: `include <foo/bar>
+sv.include system "foo/bar"