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IntelFsp2Pkg: Support FSP API to save and restore page table
A potential issue may happen when FSP creates/changes page table while bootloader doesn't expect page table being changed in FSP. Current, FSP API support to save/restore stack, IDT and general purpose registers. Following the same pattern, add save/restore page table support to solve this issue. Note that this feature only impacts FSP API mode, and is controlled by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD default value is set as FALSE. Signed-off-by: Zhiguang Liu <[email protected]>
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11 files changed

+382
-30
lines changed

11 files changed

+382
-30
lines changed

IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@
6969
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
7070
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES
7171
gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES
72+
gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable ## CONSUMES
7273

7374
[Ppis]
7475
gEfiTemporaryRamSupportPpiGuid ## PRODUCES

IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@
6868
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
6969
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES
7070
gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES
71+
gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable ## CONSUMES
7172

7273
[Ppis]
7374
gEfiTemporaryRamSupportPpiGuid ## PRODUCES

IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm

Lines changed: 29 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
1414
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
1515
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
16+
extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
1617

1718
struc FSPM_UPD_COMMON
1819
; FSP_UPD_HEADER {
@@ -64,7 +65,7 @@ extern ASM_PFX(AsmGetFspInfoHeader)
6465
extern ASM_PFX(FspMultiPhaseMemInitApiHandler)
6566

6667
STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose register * eax index
67-
API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
68+
API_PARAM1_OFFSET EQU 44h ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER + pushad + pushfd + push eax + call]
6869
FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
6970
FSP_HEADER_CFGREG_OFFSET EQU 24h
7071

@@ -153,6 +154,33 @@ NotMultiPhaseMemoryInitApi:
153154
cli
154155
pushad
155156

157+
;
158+
; Allocate 4x4 bytes on the stack.
159+
;
160+
sub esp, 16
161+
cmp byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
162+
jz SkipPagetableSave
163+
164+
add esp, 16
165+
; Save EFER MSR lower 32 bits
166+
push ecx
167+
push eax
168+
mov ecx, 0xC0000080
169+
rdmsr
170+
mov edx, eax
171+
pop eax
172+
pop ecx
173+
push edx
174+
175+
; Save CR registers
176+
mov edx, cr4
177+
push edx
178+
mov edx, cr3
179+
push edx
180+
mov edx, cr0
181+
push edx
182+
SkipPagetableSave:
183+
156184
; Reserve 8 bytes for IDT save/restore
157185
sub esp, 8
158186
sidt [esp]

IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm

Lines changed: 29 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
1414
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
1515
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
16+
extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
1617

1718
struc FSPM_UPD_COMMON
1819
; FSP_UPD_HEADER {
@@ -62,7 +63,7 @@ extern ASM_PFX(FspApiCommon)
6263
extern ASM_PFX(AsmGetFspBaseAddress)
6364
extern ASM_PFX(AsmGetFspInfoHeader)
6465

65-
API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
66+
API_PARAM1_OFFSET EQU 44h ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER +pushad + pushfd + push eax + call]
6667
FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
6768
FSP_HEADER_CFGREG_OFFSET EQU 24h
6869

@@ -124,6 +125,33 @@ ASM_PFX(FspApiCommonContinue):
124125
cli
125126
pushad
126127

128+
;
129+
; Allocate 4x4 bytes on the stack.
130+
;
131+
sub esp, 16
132+
cmp byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
133+
jz SkipPagetableSave
134+
135+
add esp, 16
136+
; Save EFER MSR lower 32-bit
137+
push ecx
138+
push eax
139+
mov ecx, 0xC0000080
140+
rdmsr
141+
mov edx, eax
142+
pop eax
143+
pop ecx
144+
push edx
145+
146+
; Save CR registers
147+
mov edx, cr4
148+
push edx
149+
mov edx, cr3
150+
push edx
151+
mov edx, cr0
152+
push edx
153+
154+
SkipPagetableSave:
127155
; Reserve 8 bytes for IDT save/restore
128156
sub esp, 8
129157
sidt [esp]

IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
55
; SPDX-License-Identifier: BSD-2-Clause-Patent
66
;;
7-
7+
DEFAULT REL
88
SECTION .text
99

1010
%include "PushPopRegsNasm.inc"
@@ -13,6 +13,7 @@
1313
; Following are fixed PCDs
1414
;
1515
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
16+
extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
1617

1718
struc FSPM_UPD_COMMON_FSP24
1819
; FSP_UPD_HEADER {
@@ -142,6 +143,36 @@ NotMultiPhaseMemoryInitApi:
142143
cli
143144
PUSHA_64
144145

146+
;
147+
; Allocate 4x8 bytes on the stack.
148+
;
149+
sub rsp, 32
150+
lea rdx, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
151+
mov dl, byte [rdx]
152+
cmp dl, 0
153+
jz SkipPagetableSave
154+
155+
add rsp, 32
156+
; Save EFER MSR
157+
push rcx
158+
push rax
159+
mov rcx, 0xC0000080
160+
rdmsr
161+
shl rdx, 0x20
162+
or rdx, rax
163+
pop rax
164+
pop rcx
165+
push rdx
166+
167+
; Save CR registers
168+
mov rdx, cr4
169+
push rdx
170+
mov rdx, cr3
171+
push rdx
172+
mov rdx, cr0
173+
push rdx
174+
SkipPagetableSave:
175+
145176
; Reserve 16 bytes for IDT save/restore
146177
sub rsp, 16
147178
sidt [rsp]

IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
55
; SPDX-License-Identifier: BSD-2-Clause-Patent
66
;;
7-
7+
DEFAULT REL
88
SECTION .text
99

1010
%include "PushPopRegsNasm.inc"
@@ -13,6 +13,7 @@
1313
; Following are fixed PCDs
1414
;
1515
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
16+
extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
1617

1718
struc FSPM_UPD_COMMON_FSP24
1819
; FSP_UPD_HEADER {
@@ -110,6 +111,36 @@ ASM_PFX(FspApiCommonContinue):
110111
cli
111112
PUSHA_64
112113

114+
;
115+
; Allocate 4x8 bytes on the stack.
116+
;
117+
sub rsp, 32
118+
lea rdx, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
119+
mov dl, byte [rdx]
120+
cmp dl, 0
121+
jz SkipPagetableSave
122+
123+
add rsp, 32
124+
; Save EFER MSR
125+
push rcx
126+
push rax
127+
mov rcx, 0xC0000080
128+
rdmsr
129+
shl rdx, 0x20
130+
or rdx, rax
131+
pop rax
132+
pop rcx
133+
push rdx
134+
135+
; Save CR registers
136+
mov rdx, cr4
137+
push rdx
138+
mov rdx, cr3
139+
push rdx
140+
mov rdx, cr0
141+
push rdx
142+
SkipPagetableSave:
143+
113144
; Reserve 16 bytes for IDT save/restore
114145
sub rsp, 16
115146
sidt [rsp]

IntelFsp2Pkg/IntelFsp2Pkg.dec

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,14 @@
114114
#
115115
gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UINT32|0x10000006
116116

117+
[PcdsFeatureFlag]
118+
#
119+
# Indicates if the FSP will save and restore page table. Only works in FSP API mode
120+
# TRUE - FSP will save and restore page table
121+
# FALSE - FSP will not save and restore page table
122+
#
123+
gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable |FALSE|BOOLEAN|0x10000007
124+
117125
[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]
118126
gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000
119127
gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT32|0x46530100

IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c

Lines changed: 8 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -15,42 +15,27 @@
1515

1616
#pragma pack(1)
1717

18-
//
19-
// API Parameter +0x34
20-
// API return address +0x30
21-
//
22-
// push FspInfoHeader +0x2C
23-
// pushfd +0x28
24-
// cli
25-
// pushad +0x24
26-
// sub esp, 8 +0x00
27-
// sidt fword ptr [esp]
28-
//
2918
typedef struct {
3019
UINT16 IdtrLimit;
3120
UINT32 IdtrBase;
3221
UINT16 Reserved;
22+
UINT32 Cr0;
23+
UINT32 Cr3;
24+
UINT32 Cr4;
25+
UINT32 Efer; // lower 32-bit of EFER since only NXE bit (BIT11) need to be restored.
3326
UINT32 Registers[8]; // General Purpose Registers: Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx and Eax
3427
UINT16 Flags[2];
3528
UINT32 FspInfoHeader;
3629
UINT32 ApiRet;
3730
UINT32 ApiParam[2];
3831
} CONTEXT_STACK;
3932

40-
//
41-
// API return address +0xB8
42-
// Reserved +0xB0
43-
// push API Parameter2 +0xA8
44-
// push API Parameter1 +0xA0
45-
// push FspInfoHeader +0x98
46-
// pushfq +0x90
47-
// cli
48-
// PUSHA_64 +0x10
49-
// sub rsp, 16 +0x00
50-
// sidt [rsp]
51-
//
5233
typedef struct {
5334
UINT64 Idtr[2]; // IDTR Limit - bit0:bi15, IDTR Base - bit16:bit79
35+
UINT64 Cr0;
36+
UINT64 Cr3;
37+
UINT64 Cr4;
38+
UINT64 Efer;
5439
UINT64 Registers[16]; // General Purpose Registers: RDI, RSI, RBP, RSP, RBX, RDX, RCX, RAX, and R15 to R8
5540
UINT32 Flags[2];
5641
UINT64 FspInfoHeader;

IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,5 +32,5 @@
3232
BaseLib
3333
IoLib
3434

35-
36-
35+
[Pcd]
36+
gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable

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