IntelFsp2Pkg: Support FSP API to save and restore page table

LiuZhiguang001 · mergify[bot] · commit 14c9ba1a2ca6 · 2024-09-11T05:45:54.000Z
A potential issue may happen when FSP creates/changes page table while
bootloader doesn't expect page table being changed in FSP.
Current, FSP API support to save/restore stack, IDT and general purpose
registers. Following the same pattern, add save/restore page table
support to solve this issue.
Note that this feature only impacts FSP API mode, and is controlled
by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD
default value is set as FALSE.

Signed-off-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -69,6 +69,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage         ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported      ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize    ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid                              ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -68,6 +68,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage         ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported      ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize    ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid                              ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -13,6 +13,7 @@
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
+extern   ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
 
 struc FSPM_UPD_COMMON
     ; FSP_UPD_HEADER {
@@ -64,7 +65,7 @@ extern ASM_PFX(AsmGetFspInfoHeader)
 extern ASM_PFX(FspMultiPhaseMemInitApiHandler)
 
 STACK_SAVED_EAX_OFFSET       EQU   4 * 7 ; size of a general purpose register * eax index
-API_PARAM1_OFFSET            EQU   34h  ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
+API_PARAM1_OFFSET            EQU   44h  ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER + pushad + pushfd + push eax + call]
 FSP_HEADER_IMGBASE_OFFSET    EQU   1Ch
 FSP_HEADER_CFGREG_OFFSET     EQU   24h
 
@@ -153,6 +154,33 @@ NotMultiPhaseMemoryInitApi:
   cli
   pushad
 
+  ;
+  ; Allocate 4x4 bytes on the stack.
+  ;
+  sub     esp, 16
+  cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
+  jz      SkipPagetableSave
+
+  add     esp, 16
+  ; Save EFER MSR lower 32 bits
+  push   ecx
+  push   eax
+  mov    ecx, 0xC0000080
+  rdmsr
+  mov    edx, eax
+  pop    eax
+  pop    ecx
+  push   edx
+
+  ; Save CR registers
+  mov    edx, cr4
+  push   edx
+  mov    edx, cr3
+  push   edx
+  mov    edx, cr0
+  push   edx
+SkipPagetableSave:
+
   ; Reserve 8 bytes for IDT save/restore
   sub     esp, 8
   sidt    [esp]
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -13,6 +13,7 @@
 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))
 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
+extern   ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
 
 struc FSPM_UPD_COMMON
     ; FSP_UPD_HEADER {
@@ -62,7 +63,7 @@ extern ASM_PFX(FspApiCommon)
 extern ASM_PFX(AsmGetFspBaseAddress)
 extern ASM_PFX(AsmGetFspInfoHeader)
 
-API_PARAM1_OFFSET            EQU   34h  ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
+API_PARAM1_OFFSET            EQU   44h  ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER +pushad + pushfd + push eax + call]
 FSP_HEADER_IMGBASE_OFFSET    EQU   1Ch
 FSP_HEADER_CFGREG_OFFSET     EQU   24h
 
@@ -124,6 +125,33 @@ ASM_PFX(FspApiCommonContinue):
   cli
   pushad
 
+  ;
+  ; Allocate 4x4 bytes on the stack.
+  ;
+  sub     esp, 16
+  cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
+  jz      SkipPagetableSave
+
+  add     esp, 16
+  ; Save EFER MSR lower 32-bit
+  push   ecx
+  push   eax
+  mov    ecx, 0xC0000080
+  rdmsr
+  mov    edx, eax
+  pop    eax
+  pop    ecx
+  push   edx
+
+  ; Save CR registers
+  mov    edx, cr4
+  push   edx
+  mov    edx, cr3
+  push   edx
+  mov    edx, cr0
+  push   edx
+
+SkipPagetableSave:
   ; Reserve 8 bytes for IDT save/restore
   sub     esp, 8
   sidt    [esp]
diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm
@@ -4,7 +4,7 @@
 ; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;;
-
+    DEFAULT REL
     SECTION .text
 
 %include    "PushPopRegsNasm.inc"
@@ -13,6 +13,7 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
+extern   ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
 
 struc FSPM_UPD_COMMON_FSP24
     ; FSP_UPD_HEADER {
@@ -142,6 +143,36 @@ NotMultiPhaseMemoryInitApi:
   cli
   PUSHA_64
 
+  ;
+  ; Allocate 4x8 bytes on the stack.
+  ;
+  sub     rsp, 32
+  lea     rdx, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
+  mov     dl, byte [rdx]
+  cmp     dl, 0
+  jz      SkipPagetableSave
+
+  add     rsp, 32
+  ; Save EFER MSR
+  push   rcx
+  push   rax
+  mov    rcx, 0xC0000080
+  rdmsr
+  shl    rdx, 0x20
+  or     rdx, rax
+  pop    rax
+  pop    rcx
+  push   rdx
+
+  ; Save CR registers
+  mov    rdx, cr4
+  push   rdx
+  mov    rdx, cr3
+  push   rdx
+  mov    rdx, cr0
+  push   rdx
+SkipPagetableSave:
+
   ; Reserve 16 bytes for IDT save/restore
   sub     rsp, 16
   sidt    [rsp]
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
@@ -4,7 +4,7 @@
 ; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;;
-
+    DEFAULT REL
     SECTION .text
 
 %include    "PushPopRegsNasm.inc"
@@ -13,6 +13,7 @@
 ; Following are fixed PCDs
 ;
 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
+extern   ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
 
 struc FSPM_UPD_COMMON_FSP24
     ; FSP_UPD_HEADER {
@@ -110,6 +111,36 @@ ASM_PFX(FspApiCommonContinue):
   cli
   PUSHA_64
 
+  ;
+  ; Allocate 4x8 bytes on the stack.
+  ;
+  sub     rsp, 32
+  lea     rdx, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
+  mov     dl, byte [rdx]
+  cmp     dl, 0
+  jz      SkipPagetableSave
+
+  add     rsp, 32
+  ; Save EFER MSR
+  push   rcx
+  push   rax
+  mov    rcx, 0xC0000080
+  rdmsr
+  shl    rdx, 0x20
+  or     rdx, rax
+  pop    rax
+  pop    rcx
+  push   rdx
+
+  ; Save CR registers
+  mov    rdx, cr4
+  push   rdx
+  mov    rdx, cr3
+  push   rdx
+  mov    rdx, cr0
+  push   rdx
+SkipPagetableSave:
+
   ; Reserve 16 bytes for IDT save/restore
   sub     rsp, 16
   sidt    [rsp]
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -114,6 +114,14 @@
   #
   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UINT32|0x10000006
 
+[PcdsFeatureFlag]
+  #
+  # Indicates if the FSP will save and restore page table. Only works in FSP API mode
+  #   TRUE  - FSP will save and restore page table
+  #   FALSE - FSP will not save and restore page table
+  #
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable |FALSE|BOOLEAN|0x10000007
+
 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]
   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength  |0x00100000|UINT32|0x46530000
   gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry          |0xFFFFFFE4|UINT32|0x46530100
diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
@@ -15,42 +15,27 @@
 
 #pragma pack(1)
 
-//
-//   API Parameter                +0x34
-//   API return address           +0x30
-//
-//   push    FspInfoHeader        +0x2C
-//   pushfd                       +0x28
-//   cli
-//   pushad                       +0x24
-//   sub     esp, 8               +0x00
-//   sidt    fword ptr [esp]
-//
 typedef struct {
   UINT16    IdtrLimit;
   UINT32    IdtrBase;
   UINT16    Reserved;
+  UINT32    Cr0;
+  UINT32    Cr3;
+  UINT32    Cr4;
+  UINT32    Efer;           // lower 32-bit of EFER since only NXE bit (BIT11) need to be restored.
   UINT32    Registers[8];   // General Purpose Registers: Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx and Eax
   UINT16    Flags[2];
   UINT32    FspInfoHeader;
   UINT32    ApiRet;
   UINT32    ApiParam[2];
 } CONTEXT_STACK;
 
-//
-//   API return address           +0xB8
-//   Reserved                     +0xB0
-//   push    API Parameter2       +0xA8
-//   push    API Parameter1       +0xA0
-//   push    FspInfoHeader        +0x98
-//   pushfq                       +0x90
-//   cli
-//   PUSHA_64                     +0x10
-//   sub     rsp, 16              +0x00
-//   sidt    [rsp]
-//
 typedef struct {
   UINT64    Idtr[2];        // IDTR Limit - bit0:bi15, IDTR Base - bit16:bit79
+  UINT64    Cr0;
+  UINT64    Cr3;
+  UINT64    Cr4;
+  UINT64    Efer;
   UINT64    Registers[16];  // General Purpose Registers: RDI, RSI, RBP, RSP, RBX, RDX, RCX, RAX, and R15 to R8
   UINT32    Flags[2];
   UINT64    FspInfoHeader;
diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
@@ -32,5 +32,5 @@
   BaseLib
   IoLib
 
-
-
+[Pcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable
diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm
diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm

-Original file line number
+Diff line change
   BaseLib
   IoLib
+-
+-
 +[Pcd]
 +  gIntelFsp2PkgTokenSpaceGuid.PcdFspSaveRestorePageTableEnable