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[Xtensa] Add LLD linker support
Closes llvm#11
1 parent 32e6411 commit ce430fd

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8 files changed

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‎lld/ELF/Arch/Xtensa.cpp

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//===- Xtensa.cpp ---------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "Symbols.h"
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#include "Target.h"
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#include <bitset>
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#include <iostream>
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#include <string>
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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class Xtensa final : public TargetInfo {
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public:
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Xtensa();
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RelExpr getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const override;
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void relocate(uint8_t *loc, const Relocation &rel,
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uint64_t val) const override;
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};
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} // namespace
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Xtensa::Xtensa() {}
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RelExpr Xtensa::getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const {
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switch (type) {
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case R_XTENSA_32:
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return R_ABS;
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case R_XTENSA_SLOT0_OP:
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// This relocation is used for various instructions, with varying ways to
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// calculate the relocation value. This is unlike most ELF architectures,
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// and is arguably bad design (see the comment on R_386_GOT32 in X86.cpp).
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// But that's what compilers emit, so it needs to be supported.
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//
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// We work around this by returning R_PC here and calculating the PC address
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// in Xtensa::relocate based on the relative value. That's ugly. A better
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// solution would be to look at the instruction here and emit various
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// Xtensa-specific RelTypes, but that has another problem: the RelExpr enum
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// is at its maximum size of 64. This will need to be fixed eventually, but
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// for now hack around it and return R_PC.
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return R_PC;
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case R_XTENSA_ASM_EXPAND:
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// This relocation appears to be emitted by the GNU Xtensa compiler as a
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// linker relaxation hint. For example, for the following code:
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//
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// .section .foo
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// .align 4
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// foo:
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// nop
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// nop
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// call0 bar
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// .align 4
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// bar:
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//
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// The call0 instruction is compiled to a l32r and callx0 instruction.
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// The LLVM Xtensa backend does not emit this relocation.
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// Because it's a relaxation hint, this relocation can be ignored for now
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// until linker relaxations are implemented.
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return R_NONE;
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case R_XTENSA_PDIFF8:
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case R_XTENSA_PDIFF16:
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case R_XTENSA_PDIFF32:
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case R_XTENSA_NDIFF8:
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case R_XTENSA_NDIFF16:
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case R_XTENSA_NDIFF32:
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// > Xtensa relocations to mark the difference of two local symbols.
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// > These are only needed to support linker relaxation and can be ignored
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// > when not relaxing.
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// Source:
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// https://github.com/espressif/binutils-gdb/commit/30ce8e47fad9b057b6d7af9e1d43061126d34d20:
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// Because we don't do linker relaxation, we can ignore these relocations.
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return R_NONE;
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default:
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error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
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") against symbol " + toString(s));
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return R_NONE;
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}
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}
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static inline bool isRRI8Branch(uint8_t *loc) {
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if ((loc[0] & 0x0f) == 0b0111) {
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// instructions: ball, bany, bbc, bbci, bbs, bbsi, beq, bge, bgeu, blt,
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// bltu, bnall, bne, bnone
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return true;
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}
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if ((loc[0] & 0b11'1111) == 0b10'0110) {
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// instructions: beqi, bgei, bnei, blti
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return true;
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}
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if ((loc[0] & 0b1011'1111) == 0b1011'0110) {
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// instructions: bgeui, bltui
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return true;
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}
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// some other instruction
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return false;
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}
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void Xtensa::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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switch (rel.type) {
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case R_XTENSA_32:
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write32le(loc, val);
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break;
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case R_XTENSA_SLOT0_OP: {
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// HACK: calculate the instruction location based on the PC-relative
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// relocation value.
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uint64_t dest = rel.sym->getVA(rel.addend);
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uint64_t p = dest - val;
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// This relocation is used for various instructions.
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// Look at the instruction to determine how to do the relocation.
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uint8_t opcode = loc[0] & 0x0f;
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if (opcode == 0b0001) { // RI16 format: l32r
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uint64_t val = dest - ((p + 3) & (uint64_t)0xfffffffc);
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checkInt(loc, static_cast<int64_t>(val) >> 2, 16, rel);
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checkAlignment(loc, val, 4, rel);
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write16le(loc + 1, static_cast<int64_t>(val) >> 2);
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} else if (opcode == 0b0101) { // call0, call4, call8, call12 (CALL format)
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uint64_t val = dest - ((p + 4) & (uint64_t)0xfffffffc);
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checkInt(loc, static_cast<int64_t>(val) >> 2, 18, rel);
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checkAlignment(loc, val, 4, rel);
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const int64_t target = static_cast<int64_t>(val) >> 2;
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loc[0] = (loc[0] & 0b0011'1111) | ((target & 0b0000'0011) << 6);
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loc[1] = target >> 2;
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loc[2] = target >> 10;
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} else if ((loc[0] & 0x3f) == 0b00'0110) { // j (CALL format)
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uint64_t val = dest - p + 4;
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checkInt(loc, static_cast<int64_t>(val), 18, rel);
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loc[0] = (loc[0] & 0b0011'1111) | ((val & 0b0000'0011) << 6);
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loc[1] = val >> 2;
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loc[2] = val >> 10;
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} else if (isRRI8Branch(loc)) { // RRI8 format (various branch instructions)
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uint64_t v = val - 4;
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checkInt(loc, static_cast<int64_t>(v), 8, rel);
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loc[2] = v & 0xff;
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} else if ((loc[0] & 0b1000'1111) == 0b1000'1100) { // RI16 format: beqz.n, bnez.n
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uint64_t v = val - 4;
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checkUInt(loc, v, 6, rel);
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loc[0] = (loc[0] & 0xcf) | (v & 0x30);
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loc[1] = (loc[1] & 0x0f) | ((v & 0x0f) << 4);
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} else if ((loc[0] & 0b0011'1111) == 0b0001'0110) { // BRI12 format: beqz, bgez, bltz, bnez
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uint64_t v = val - 4;
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checkInt(loc, static_cast<int64_t>(v), 12, rel);
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loc[1] = ((loc[1] & 0x0f)) | ((v & 0x0f) << 4);
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loc[2] = (v >> 4) & 0xff;
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} else {
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error(getErrorLocation(loc) +
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"unknown opcode for relocation: " + std::to_string(loc[0]));
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}
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break;
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}
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default:
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llvm_unreachable("unknown relocation");
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}
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}
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TargetInfo *elf::getXtensaTargetInfo() {
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static Xtensa target;
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return &target;
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}

‎lld/ELF/CMakeLists.txt

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@@ -22,6 +22,7 @@ add_lld_library(lldELF
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Arch/SPARCV9.cpp
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Arch/X86.cpp
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Arch/X86_64.cpp
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Arch/Xtensa.cpp
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ARMErrataFix.cpp
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CallGraphSort.cpp
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DWARF.cpp

‎lld/ELF/InputFiles.cpp

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@@ -1538,6 +1538,8 @@ static uint16_t getBitcodeMachineKind(StringRef path, const Triple &t) {
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return t.isOSIAMCU() ? EM_IAMCU : EM_386;
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case Triple::x86_64:
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return EM_X86_64;
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case Triple::xtensa:
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return EM_XTENSA;
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default:
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error(path + ": could not infer e_machine from bitcode target triple " +
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t.str());

‎lld/ELF/Target.cpp

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@@ -87,6 +87,8 @@ TargetInfo *elf::getTarget() {
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return getSPARCV9TargetInfo();
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case EM_X86_64:
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return getX86_64TargetInfo();
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case EM_XTENSA:
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return getXtensaTargetInfo();
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}
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llvm_unreachable("unknown target machine");
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}

‎lld/ELF/Target.h

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@@ -187,6 +187,7 @@ TargetInfo *getRISCVTargetInfo();
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TargetInfo *getSPARCV9TargetInfo();
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TargetInfo *getX86TargetInfo();
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TargetInfo *getX86_64TargetInfo();
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TargetInfo *getXtensaTargetInfo();
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template <class ELFT> TargetInfo *getMipsTargetInfo();
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struct ErrorPlace {

‎lld/test/ELF/xtensa-reloc.s

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# REQUIRES: xtensa
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# RUN: llvm-mc -filetype=obj -triple=xtensa -mcpu=esp32 %s -o %t.o
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# RUN: ld.lld %t.o --defsym=a=0x2000 --section-start=.CALL=0x1000 --defsym=b=40 -o %t
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# RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s
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.section .CALL,"ax",@progbits
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# CHECK-LABEL: section .CALL:
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# CHECK: call0 . +4096
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# CHECK-NEXT: call0 . +4096
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# CHECK-NEXT: call0 . +4092
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# CHECK-NEXT: call0 . +4088
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# CHECK-NEXT: call0 . -4068
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call0 a
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call0 a
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call0 a
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call0 a
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call0 b

‎lld/test/lit.cfg.py

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@@ -74,7 +74,8 @@
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'RISCV': 'riscv',
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'Sparc': 'sparc',
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'WebAssembly': 'wasm',
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'X86': 'x86'}),
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'X86': 'x86',
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'Xtensa': 'xtensa'}),
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('--assertion-mode', {'ON': 'asserts'}),
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])
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‎llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def

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@@ -57,3 +57,9 @@ ELF_RELOC(R_XTENSA_TLS_TPOFF, 53)
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ELF_RELOC(R_XTENSA_TLS_FUNC, 54)
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ELF_RELOC(R_XTENSA_TLS_ARG, 55)
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ELF_RELOC(R_XTENSA_TLS_CALL, 56)
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ELF_RELOC(R_XTENSA_PDIFF8, 57)
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ELF_RELOC(R_XTENSA_PDIFF16, 58)
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ELF_RELOC(R_XTENSA_PDIFF32, 59)
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ELF_RELOC(R_XTENSA_NDIFF8, 60)
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ELF_RELOC(R_XTENSA_NDIFF16, 61)
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ELF_RELOC(R_XTENSA_NDIFF32, 62)

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