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[AMDGPU] Remove wavefrontsize feature from GFX10+ (llvm#98400)
Processor definition shall not include a default feature which may be switched off by a different wave size. This allows not to write -mattr=-wavefrontsize32,+wavefrontsize64 in tests.
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10 files changed

+377
-349
lines changed

10 files changed

+377
-349
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

-3
Original file line numberDiff line numberDiff line change
@@ -1464,7 +1464,6 @@ def FeatureISAVersion10_Common : FeatureSet<
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FeatureLDSBankCount32,
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FeatureDLInsts,
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FeatureNSAEncoding,
1467-
FeatureWavefrontSize32,
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FeatureBackOffBarrier]>;
14691468

14701469
def FeatureISAVersion10_1_Common : FeatureSet<
@@ -1548,7 +1547,6 @@ def FeatureISAVersion11_Common : FeatureSet<
15481547
FeatureDot10Insts,
15491548
FeatureNSAEncoding,
15501549
FeaturePartialNSAEncoding,
1551-
FeatureWavefrontSize32,
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FeatureShaderCyclesRegister,
15531551
FeatureArchitectedFlatScratch,
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FeatureAtomicFaddRtnInsts,
@@ -1625,7 +1623,6 @@ def FeatureISAVersion12 : FeatureSet<
16251623
FeatureDot11Insts,
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FeatureNSAEncoding,
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FeaturePartialNSAEncoding,
1628-
FeatureWavefrontSize32,
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FeatureShaderCyclesHiLoRegisters,
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FeatureArchitectedFlatScratch,
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FeatureArchitectedSGPRs,

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

+8
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,14 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
105105
: AMDGPUSubtarget::SOUTHERN_ISLANDS;
106106
}
107107

108+
if (!hasFeature(AMDGPU::FeatureWavefrontSize32) &&
109+
!hasFeature(AMDGPU::FeatureWavefrontSize64)) {
110+
// If there is no default wave size it must be a generation before gfx10,
111+
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
112+
// set wave32 as a default.
113+
ToggleFeature(AMDGPU::FeatureWavefrontSize32);
114+
}
115+
108116
// We don't support FP64 for EG/NI atm.
109117
assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS));
110118

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

+9
Original file line numberDiff line numberDiff line change
@@ -1408,6 +1408,15 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
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copySTI().ToggleFeature("southern-islands");
14091409
}
14101410

1411+
FeatureBitset FB = getFeatureBits();
1412+
if (!FB[AMDGPU::FeatureWavefrontSize64] &&
1413+
!FB[AMDGPU::FeatureWavefrontSize32]) {
1414+
// If there is no default wave size it must be a generation before gfx10,
1415+
// these have FeatureWavefrontSize64 in their definition already. For
1416+
// gfx10+ set wave32 as a default.
1417+
copySTI().ToggleFeature(AMDGPU::FeatureWavefrontSize32);
1418+
}
1419+
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setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
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AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

+18-2
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,26 @@ using namespace llvm;
4545

4646
using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
4747

48+
static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
49+
MCContext &Ctx) {
50+
if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
51+
!STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
52+
MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
53+
// If there is no default wave size it must be a generation before gfx10,
54+
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
55+
// set wave32 as a default.
56+
STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
57+
return STICopy;
58+
}
59+
60+
return STI;
61+
}
62+
4863
AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
4964
MCContext &Ctx, MCInstrInfo const *MCII)
50-
: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
51-
MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
65+
: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
66+
MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
67+
TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
5268
CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
5369
// ToDo: AMDGPUDisassembler supports only VI ISA.
5470
if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())

‎llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,-wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
2-
; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,-wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
31
; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
42
; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
53

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll

+8-8
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,19 @@
11
; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
2-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W32 %s
3-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,W32 %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
2+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W32 %s
3+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,W32 %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
66

77
; RUN: opt -O3 -S < %s | FileCheck -check-prefix=OPT %s
88
; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefix=OPT %s
99
; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
1010
; RUN: opt -mtriple=amdgcn-- -passes='default<O3>' -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
1111
; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
1212
; RUN: opt -mtriple=amdgcn-- -mcpu=tonga -O3 -S < %s | FileCheck -check-prefix=OPT %s
13-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=+wavefrontsize32,-wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
14-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=-wavefrontsize32,+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
15-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=+wavefrontsize32,-wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
16-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=-wavefrontsize32,+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
13+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
14+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
15+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
16+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
1717

1818
; GCN-LABEL: {{^}}fold_wavefrontsize:
1919
; OPT-LABEL: define amdgpu_kernel void @fold_wavefrontsize(

‎llvm/test/CodeGen/AMDGPU/unknown-processor.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: not llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
1+
; RUN: llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
22
; RUN: llc -mtriple=r600-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s
33
target datalayout = "A5"
44

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