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Add some circuits #44
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No need to push any assets, just the typst or latex source code and a YAML file with metadata like |
I guess I am happy with that for now, how often does the website update? |
usually after every commit/merge but it's currently failing because of an incompatibility issue in one of the imported packages: janosh/svelte-multiselect#295. was planning to work on that last weekend but didn't manage, hopefully next one |
I saw your changes to my functions thank you, for grouping them like that, I have a patch for the hop function Details
#let wire_hop(
wire1_start, wire1_end,
wire2_start, wire2_end,
hopping_wire: 1,
hop_radius: 0.15,
hop_direction: 1,
..styling
) = {
assert(hopping_wire in (1, 2), message: "hopping_wire must be 1 or 2.")
assert(hop_direction in (1, -1), message: "hop_direction must be 1 or -1.")
cetz.draw.get-ctx(ctx=>{
let a1=cetz.coordinate.resolve(ctx,wire1_start).at(1)
let a2=cetz.coordinate.resolve(ctx,wire1_end).at(1)
let b1=cetz.coordinate.resolve(ctx,wire2_start).at(1)
let b2=cetz.coordinate.resolve(ctx,wire2_end).at(1)
let intersection = cetz.intersection.line-line(
(a1.at(0),a1.at(1)), (a2.at(0),a2.at(1)),
(b1.at(0),b1.at(1)), (b2.at(0),b2.at(1)),
)
//cetz.draw.content((0,0))[#intersection]
//cetz.coordinate.resolve(ctx,wire2_end)
// /*
assert(intersection != none, message: "Wires do not intersect, cannot hop.")
let (straight_start, straight_end, hopping_start, hopping_end) = if hopping_wire == 1 {
(b1, b2, a1, a2)
} else {
(a1, a2, b1, b2)
}
cetz.draw.line(straight_start, straight_end, ..styling)
let hop_vec = cetz.vector.sub(hopping_end, hopping_start)
// cetz.draw.content((0,0))[#hop_vec]
// /*
let wire_angle = calc.atan2(hop_vec.at(0),hop_vec.at(1))
let hop_unit_vec = cetz.vector.norm(hop_vec)
assert(hop_unit_vec != none, message: "Cannot get unit vector for zero-length hopping wire.")
let offset_vec_neg = cetz.vector.scale(hop_unit_vec, -hop_radius)
let offset_vec_pos = cetz.vector.scale(hop_unit_vec, hop_radius)
let arc_start_point = (rel: offset_vec_neg, to: intersection)
let arc_end_point = (rel: offset_vec_pos, to: intersection)
let arc_start_angle = wire_angle
let arc_stop_angle = wire_angle + (180deg *hop_direction)
cetz.draw.line(hopping_start, arc_start_point, ..styling)
cetz.draw.arc(
(rel:cetz.vector.scale((calc.cos(arc_start_angle),calc.sin(arc_start_angle)),hop_radius*2),to:arc_start_point),
start: arc_start_angle,
stop: arc_stop_angle,
radius: hop_radius,
..styling
)
cetz.draw.line(arc_end_point, hopping_end, ..styling)
// */
})
} assuming you used something like components.typ
#import "./components.typ" as comp
#cetz.canvas({
let default_stroke = (stroke: (thickness: 0.6pt))
let node_style = (fill: black, radius: 0.05pt)
let x_in_labels = -1
let x_transistors = 0
let x_out_label = 2
let y_vdd = 4.4
let y_m3_base = 3.0
let y_m2_base = 1.0
let y_m1_base = -0.5
let y_gnd = -1.5
let pt_vin_label = (x_in_labels, 0)
let pt_vbias_label = (x_in_labels, 1.6)
let pt_vout_label = (x_out_label+1, 2.2)
let pt_vdd_connect = (x_transistors, y_vdd)
let pt_gnd_connect = (x_transistors, y_gnd)
comp.vdd_symbol(pt_vdd_connect, "VddSym", label: $V_"DD"$, label_offset:(0, 0.3), ..default_stroke)
comp.gnd_symbol(pt_gnd_connect, "GndSym", ..default_stroke)
comp.nmos_transistor((x_transistors, y_m1_base), "M1", label: $M_1$, label_pos: "west", label_offset: (0.5, 0.3), ..default_stroke,bulk_lead_factor:-0.6)
comp.nmos_transistor((x_transistors, y_m2_base), "M2", label: $M_2$, label_pos: "west", label_offset: (0.5, 0.3), ..default_stroke,bulk_lead_factor:-0.6)
comp.pmos_transistor((x_transistors+1.8, y_m3_base), "M3", label: $M_3$, label_pos: "west", label_offset: (-1.0, -0.0), ..default_stroke,width:-0.9,bulk_lead_factor:-0.6)
comp.node(pt_vin_label, "VinNode", label: $V_"in"$, label_anchor: "east", label_offset: (-0.2, 0))
comp.node(pt_vbias_label, "VbiasNode", label: $V_"bias"$, label_anchor: "east", label_offset: (-0.2, 0))
comp.node(pt_vout_label, "VoutNode", label: $V_"out"$, label_anchor: "west", label_offset: (0.2, 0))
comp.connect-orthogonal("VinNode", "M1.G", style: "hv", ..default_stroke)
comp.connect-orthogonal("VbiasNode", "M2.G", style: "hv", ..default_stroke)
comp.connect-orthogonal("VddSym.B", "M3.S", style: "vh", ..default_stroke)
comp.connect-orthogonal("M1.S", "GndSym.T", style: "vh", ..default_stroke)
comp.connect-orthogonal("M1.D", "M2.S", style: "vh", ..default_stroke)
comp.connect-orthogonal("M2.D", "M3.D", style: "vh", ..default_stroke)
comp.wire_hop(
(rel:(0,0),to:"M3.G"), (rel:(1.16,0),to:"M1.D"),
"M2.D", "VoutNode",
hopping_wire: 1,
hop_radius: 0.1,
hop_direction: 1,
..default_stroke
)
comp.connect-orthogonal("M1.D", (rel:(1.16,0),to:"M1.D"), style: "vh", ..default_stroke)
}) would look like note: pmos needs a hack |
looks great! we could think about starting a Typst component system in this repo e.g. in a new folder |
problem with that is that examples are no longer copy pasteable. no? aka to play for example on typst web |
yes, that's true. i was thinking about how hard it would be to inline local imports on the website such that code can still be copy-pasted without having to piece together different parts of the repo. could be quite hard. which is why i'm not strongly advocating for that but don't want to block it either without trying. still, would be less work for now to keep self-contained diagrams |
I think imho the best deal is, we, for now keep every diagram self contained (even if it comes at the cost of repetitions), and when there is enough repetition, it is possible to build a symbol gallery as a library. |
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I would do a PR but it seems actions are failing and it is confusing, do we have to also upload the SVG shouldn't that be part of the actions themselves?
Details
maybe you like timed event graphs
Details
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