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Remove special handling of zero registers in relation analysis
Signed-off-by: Hernan Ponce de Leon <[email protected]>
1 parent 4a0bc2c commit 9a58fa2

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-31
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dartagnan/src/main/java/com/dat3m/dartagnan/wmm/analysis/LazyRelationAnalysis.java

-20
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
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import com.dat3m.dartagnan.program.analysis.ReachingDefinitionsAnalysis;
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import com.dat3m.dartagnan.program.analysis.alias.AliasAnalysis;
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import com.dat3m.dartagnan.program.event.Event;
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import com.dat3m.dartagnan.program.event.RegReader;
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import com.dat3m.dartagnan.program.event.Tag;
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import com.dat3m.dartagnan.program.event.core.*;
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import com.dat3m.dartagnan.program.filter.Filter;
@@ -33,7 +32,6 @@
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import java.util.concurrent.ConcurrentHashMap;
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import java.util.stream.Collectors;
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import static com.dat3m.dartagnan.configuration.Arch.RISCV;
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import static com.dat3m.dartagnan.program.Register.UsageType.*;
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import static com.dat3m.dartagnan.program.event.Tag.FENCE;
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import static com.dat3m.dartagnan.program.event.Tag.VISIBLE;
@@ -233,24 +231,6 @@ public RelationAnalysis.Knowledge visitInternalDataDependency(DirectDataDependen
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private EventGraph computeInternalDependencies(Set<Register.UsageType> usageTypes) {
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Map<Event, Set<Event>> data = new HashMap<>();
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program.getThreadEvents(RegReader.class).forEach(reader -> {
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ReachingDefinitionsAnalysis.Writers state = definitions.getWriters(reader);
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reader.getRegisterReads().forEach(read -> {
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if (usageTypes.contains(read.usageType())) {
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Register register = read.register();
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// TODO: Update after this is merged
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// https://github.com/hernanponcedeleon/Dat3M/pull/741
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// Register x0 is hardwired to the constant 0 in RISCV
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// https://en.wikichip.org/wiki/risc-v/registers,
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// and thus it generates no dependency, see
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// https://github.com/herd/herdtools7/issues/408
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if (!program.getArch().equals(RISCV) || !register.getName().equals("x0")) {
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state.ofRegister(register).getMayWriters().forEach(writer ->
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data.computeIfAbsent(writer, x -> new HashSet<>()).add(reader));
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}
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}
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});
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});
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if (usageTypes.contains(DATA)) {
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program.getThreadEvents(ExecutionStatus.class).forEach(execStatus -> {
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if (execStatus.doesTrackDep()) {

dartagnan/src/main/java/com/dat3m/dartagnan/wmm/analysis/NativeRelationAnalysis.java

-11
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,6 @@
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import java.util.stream.Collectors;
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import java.util.stream.Stream;
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import static com.dat3m.dartagnan.configuration.Arch.RISCV;
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import static com.dat3m.dartagnan.program.Register.UsageType.*;
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import static com.dat3m.dartagnan.program.event.Tag.*;
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import static com.google.common.base.Preconditions.checkArgument;
@@ -915,16 +914,6 @@ private MutableKnowledge computeInternalDependencies(Set<UsageType> usageTypes)
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continue;
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}
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final Register register = regRead.register();
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// TODO: Update after this is merged
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// https://github.com/hernanponcedeleon/Dat3M/pull/741
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// Register x0 is hardwired to the constant 0 in RISCV
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// https://en.wikichip.org/wiki/risc-v/registers,
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// and thus it generates no dependency, see
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// https://github.com/herd/herdtools7/issues/408
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// TODO: Can't we just replace all reads of "x0" by 0 in RISC-specific preprocessing?
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if (program.getArch().equals(RISCV) && register.getName().equals("x0")) {
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continue;
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}
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final List<? extends Event> writers = state.ofRegister(register).getMayWriters();
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for (Event regWriter : writers) {
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may.add(regWriter, regReader);

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