Ensure that AdvSimd.Insert doesn't zero out the upper bits (#107091)

Co-authored-by: Tanner Gooding <[email protected]>

Author: github-actions[bot]

src/coreclr/jit/hwintrinsiccodegenarm64.cpp

@@ -610,44 +610,38 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
             break;
 
             case NI_AdvSimd_Insert:
+            {
                 assert(isRMW);
 
                 GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
 
-                if (intrin.op3->isContainedFltOrDblImmed())
-                {
-                    assert(intrin.op2->isContainedIntOrIImmed());
-                    assert(intrin.op2->AsIntCon()->gtIconVal == 0);
+                // fmov (scalar) zeros the upper bits and is not safe to use
+                assert(!intrin.op3->isContainedFltOrDblImmed());
 
-                    const double dataValue = intrin.op3->AsDblCon()->DconValue();
-                    GetEmitter()->emitIns_R_F(INS_fmov, emitSize, targetReg, dataValue, opt);
-                }
-                else
-                {
-                    assert(targetReg != op3Reg);
+                assert(targetReg != op3Reg);
 
-                    HWIntrinsicImmOpHelper helper(this, intrin.op2, node);
+                HWIntrinsicImmOpHelper helper(this, intrin.op2, node);
 
-                    if (varTypeIsFloating(intrin.baseType))
+                if (varTypeIsFloating(intrin.baseType))
+                {
+                    for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
                     {
-                        for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
-                        {
-                            const int elementIndex = helper.ImmValue();
+                        const int elementIndex = helper.ImmValue();
 
-                            GetEmitter()->emitIns_R_R_I_I(ins, emitSize, targetReg, op3Reg, elementIndex, 0, opt);
-                        }
+                        GetEmitter()->emitIns_R_R_I_I(ins, emitSize, targetReg, op3Reg, elementIndex, 0, opt);
                     }
-                    else
+                }
+                else
+                {
+                    for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
                     {
-                        for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
-                        {
-                            const int elementIndex = helper.ImmValue();
+                        const int elementIndex = helper.ImmValue();
 
-                            GetEmitter()->emitIns_R_R_I(ins, emitSize, targetReg, op3Reg, elementIndex, opt);
-                        }
+                        GetEmitter()->emitIns_R_R_I(ins, emitSize, targetReg, op3Reg, elementIndex, opt);
                     }
                 }
                 break;
+            }
 
             case NI_AdvSimd_InsertScalar:
             {

src/coreclr/jit/lowerarmarch.cpp

@@ -2819,18 +2819,6 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
                 if (intrin.op2->IsCnsIntOrI())
                 {
                     MakeSrcContained(node, intrin.op2);
-
-                    if ((intrin.op2->AsIntCon()->gtIconVal == 0) && intrin.op3->IsCnsFltOrDbl())
-                    {
-                        assert(varTypeIsFloating(intrin.baseType));
-
-                        const double dataValue = intrin.op3->AsDblCon()->DconValue();
-
-                        if (comp->GetEmitter()->emitIns_valid_imm_for_fmov(dataValue))
-                        {
-                            MakeSrcContained(node, intrin.op3);
-                        }
-                    }
                 }
                 break;
 

src/tests/JIT/Regression/JitBlue/Runtime_106079/Runtime_106079.cs

@@ -0,0 +1,28 @@
+// Licensed to the .NET Foundation under one or more agreements.
+// The .NET Foundation licenses this file to you under the MIT license.
+
+using System;
+using System.Runtime.CompilerServices;
+using System.Numerics;
+using System.Runtime.Intrinsics;
+using System.Runtime.Intrinsics.Arm;
+using Xunit;
+
+// Generated by Fuzzlyn v2.2 on 2024-08-06 15:11:52
+// Run on Arm64 MacOS
+// Seed: 289142602786847481-vectort,vector64,vector128,armadvsimd,armadvsimdarm64,armaes,armarmbase,armarmbasearm64,armcrc32,armcrc32arm64,armdp,armrdm,armrdmarm64,armsha1,armsha256
+// Reduced from 87.5 KiB to 0.4 KiB in 00:00:36
+// Debug: Outputs <4607182418800017408, 13871573557235963454>
+// Release: Outputs <4607182418800017408, 0>
+
+public class Runtime_106079
+{
+    private static Vector128<double> s_38 = Vector128.Create(0, -567.3319449449843d);
+
+    public static void TestEntryPoint()
+    {
+        double vr4 = 1;
+        s_38 = AdvSimd.Insert(s_38, 0, vr4);
+        Assert.Equal(Vector128.Create(4607182418800017408UL, 13871573557235963454UL), s_38.AsUInt64());
+    }
+}

src/tests/JIT/Regression/JitBlue/Runtime_106079/Runtime_106079.csproj

@@ -0,0 +1,8 @@
+<Project Sdk="Microsoft.NET.Sdk">
+  <PropertyGroup>
+    <Optimize>True</Optimize>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="$(MSBuildProjectName).cs" />
+  </ItemGroup>
+</Project>