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khushal1996Ruihan-YinBruceForstall
authored
Add support for AVX10.2, Add AVX10.2 API surface and template tests (#111209)
* Add support for AVX10.2. Add AVX10.2 API surface and template tests. Lower Avx10.2 nodes accordingly. * Add support and template tests for AVX10v2_V512 * Add new coredistools.dll build from latest llvm repo * Limit JIT unit suite within the subsets which are stable in SDE. * Rename API as per latest API proposal discussions * fix sample tests in handwritten project * Revert "Limit JIT unit suite within the subsets which are stable in SDE." This reverts commit 067e31e. * Limit JIT unit suite within the subsets which are stable in SDE. * Allow a prefix of 0x00 for AVX10.2 instructions. * Revert "Limit JIT unit suite within the subsets which are stable in SDE." This reverts commit 067e31e. * Limit JIT unit suite within the subsets which are stable in SDE. * remove developer comments from files * Enable all template tests and enable ymm embedded rounding * Make emitter independent of ISa and based on insOpts for ymm embedded rounding * Enable ymm embedded rounding based on architecture * Revert "Make emitter independent of ISa and based on insOpts for ymm embedded rounding" This reverts commit 493572f. * Separate Avx10.2 unit testing framework from APX framework * Revert "Limit JIT unit suite within the subsets which are stable in SDE." This reverts commit 067e31e. * Revert "Add new coredistools.dll build from latest llvm repo" This reverts commit 61719f8. * Fix formatting * Use new keyword for class V512 to hide Avx10v1.V512 and correct CI errors * Remove MinMax APis from lowering for numargs=2 * Add docstrings for APIs * revert changes for sde execution of tests * Add appropriate comments from reviews * Apply suggestions from code review Co-authored-by: Bruce Forstall <[email protected]> * Add emitter tests for XMM9/16 to make sure special handling does not interfere. * Format code * Handle sizePrefix = 0 case when decoding evex instruction * Add assert in appropriate places * Club similar instructions together in perf calculation in emitxarch * Run formatting * Add assembly prints for debug assembly capturing for Avx10.2 * Use correct size when running emitter tests * Ad appropriate comments and make review changes * Apply suggestions from code review Co-authored-by: Bruce Forstall <[email protected]> --------- Co-authored-by: Ruihan-Yin <[email protected]> Co-authored-by: Bruce Forstall <[email protected]>
1 parent 6b55713 commit 03b2d3d

37 files changed

+2092
-166
lines changed

‎src/coreclr/jit/codegen.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -650,6 +650,7 @@ class CodeGen final : public CodeGenInterface
650650
#if defined(TARGET_AMD64)
651651
void genAmd64EmitterUnitTestsSse2();
652652
void genAmd64EmitterUnitTestsApx();
653+
void genAmd64EmitterUnitTestsAvx10v2();
653654
#endif
654655

655656
#endif // defined(DEBUG)

‎src/coreclr/jit/codegencommon.cpp

Lines changed: 28 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1832,15 +1832,26 @@ void CodeGen::genGenerateMachineCode()
18321832
#if defined(TARGET_X86)
18331833
if (compiler->canUseEvexEncoding())
18341834
{
1835-
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v1))
1835+
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2))
1836+
{
1837+
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512))
1838+
{
1839+
printf("X86 with AVX10.2/512");
1840+
}
1841+
else
1842+
{
1843+
printf("X86 with AVX10.2/256");
1844+
}
1845+
}
1846+
else if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v1))
18361847
{
18371848
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v1_V512))
18381849
{
1839-
printf("X86 with AVX10/512");
1850+
printf("X86 with AVX10.1/512");
18401851
}
18411852
else
18421853
{
1843-
printf("X86 with AVX10/256");
1854+
printf("X86 with AVX10.1/256");
18441855
}
18451856
}
18461857
else
@@ -1860,15 +1871,26 @@ void CodeGen::genGenerateMachineCode()
18601871
#elif defined(TARGET_AMD64)
18611872
if (compiler->canUseEvexEncoding())
18621873
{
1863-
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v1))
1874+
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2))
1875+
{
1876+
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512))
1877+
{
1878+
printf("X64 with AVX10.2/512");
1879+
}
1880+
else
1881+
{
1882+
printf("X64 with AVX10.2/256");
1883+
}
1884+
}
1885+
else if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v1))
18641886
{
18651887
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v1_V512))
18661888
{
1867-
printf("X64 with AVX10/512");
1889+
printf("X64 with AVX10.1/512");
18681890
}
18691891
else
18701892
{
1871-
printf("X64 with AVX10/256");
1893+
printf("X64 with AVX10.1/256");
18721894
}
18731895
}
18741896
else

‎src/coreclr/jit/codegenlinear.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2712,6 +2712,10 @@ void CodeGen::genEmitterUnitTests()
27122712
{
27132713
genAmd64EmitterUnitTestsApx();
27142714
}
2715+
if (unitTestSectionAll || (strstr(unitTestSection, "avx10v2") != nullptr))
2716+
{
2717+
genAmd64EmitterUnitTestsAvx10v2();
2718+
}
27152719

27162720
#elif defined(TARGET_ARM64)
27172721
if (unitTestSectionAll || (strstr(unitTestSection, "general") != nullptr))

‎src/coreclr/jit/codegenxarch.cpp

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9239,6 +9239,159 @@ void CodeGen::genAmd64EmitterUnitTestsApx()
92399239
theEmitter->emitIns_S(INS_not, EA_2BYTE, 0, 0);
92409240
}
92419241

9242+
void CodeGen::genAmd64EmitterUnitTestsAvx10v2()
9243+
{
9244+
// All the Avx10.2 instructions are evex and evex only has one size.
9245+
// Also, there is no specialized handling for XMM0 vs XMM9 vs XMM16
9246+
9247+
emitter* theEmitter = GetEmitter();
9248+
9249+
genDefineTempLabel(genCreateTempLabel());
9250+
9251+
// This test suite needs AVX10.2 enabled.
9252+
if (!theEmitter->emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2))
9253+
{
9254+
return;
9255+
}
9256+
9257+
// packed conversion instructions
9258+
theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_16BYTE, REG_XMM0, REG_XMM1); // xmm
9259+
theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_16BYTE, REG_XMM9, REG_XMM10); // xmm
9260+
theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_16BYTE, REG_XMM15, REG_XMM16); // xmm
9261+
theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm
9262+
theEmitter->emitIns_R_R(INS_vcvttps2dqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm
9263+
9264+
theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_16BYTE, REG_XMM0, REG_XMM1); // xmm
9265+
theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_16BYTE, REG_XMM9, REG_XMM10); // xmm
9266+
theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_16BYTE, REG_XMM15, REG_XMM16); // xmm
9267+
theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm
9268+
theEmitter->emitIns_R_R(INS_vcvttps2udqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm
9269+
9270+
theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_16BYTE, REG_XMM0, REG_XMM1); // xmm
9271+
theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_16BYTE, REG_XMM9, REG_XMM10); // xmm
9272+
theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_16BYTE, REG_XMM15, REG_XMM16); // xmm
9273+
theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm
9274+
theEmitter->emitIns_R_R(INS_vcvttpd2qqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm
9275+
9276+
theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_16BYTE, REG_XMM0, REG_XMM1); // xmm
9277+
theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_16BYTE, REG_XMM9, REG_XMM10); // xmm
9278+
theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_16BYTE, REG_XMM15, REG_XMM16); // xmm
9279+
theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_32BYTE, REG_XMM0, REG_XMM1); // ymm
9280+
theEmitter->emitIns_R_R(INS_vcvttpd2uqqs, EA_64BYTE, REG_XMM0, REG_XMM1); // zmm
9281+
9282+
// scalar conversion instructions
9283+
theEmitter->emitIns_R_R(INS_vcvttsd2sis32, EA_4BYTE, REG_EAX, REG_XMM0);
9284+
theEmitter->emitIns_R_R(INS_vcvttsd2sis64, EA_8BYTE, REG_RAX, REG_XMM0);
9285+
theEmitter->emitIns_R_R(INS_vcvttsd2usis32, EA_4BYTE, REG_EAX, REG_XMM0);
9286+
theEmitter->emitIns_R_R(INS_vcvttsd2usis64, EA_8BYTE, REG_RAX, REG_XMM0);
9287+
theEmitter->emitIns_R_R(INS_vcvttss2sis32, EA_4BYTE, REG_EAX, REG_XMM0);
9288+
theEmitter->emitIns_R_R(INS_vcvttss2sis64, EA_8BYTE, REG_RAX, REG_XMM0);
9289+
theEmitter->emitIns_R_R(INS_vcvttss2usis32, EA_4BYTE, REG_EAX, REG_XMM0);
9290+
theEmitter->emitIns_R_R(INS_vcvttss2usis64, EA_8BYTE, REG_RAX, REG_XMM0);
9291+
9292+
// minmax instruction
9293+
theEmitter->emitIns_R_R_R_I(INS_vminmaxss, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);
9294+
theEmitter->emitIns_R_R_R_I(INS_vminmaxss, EA_16BYTE, REG_XMM8, REG_XMM9, REG_XMM10, 0);
9295+
theEmitter->emitIns_R_R_R_I(INS_vminmaxss, EA_16BYTE, REG_XMM14, REG_XMM15, REG_XMM16, 0);
9296+
9297+
theEmitter->emitIns_R_R_R_I(INS_vminmaxsd, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);
9298+
theEmitter->emitIns_R_R_R_I(INS_vminmaxsd, EA_16BYTE, REG_XMM9, REG_XMM10, REG_XMM11, 0);
9299+
theEmitter->emitIns_R_R_R_I(INS_vminmaxsd, EA_16BYTE, REG_XMM16, REG_XMM17, REG_XMM18, 0);
9300+
9301+
theEmitter->emitIns_R_R_R_I(INS_vminmaxps, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);
9302+
theEmitter->emitIns_R_R_R_I(INS_vminmaxpd, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);
9303+
theEmitter->emitIns_R_R_R_I(INS_vminmaxps, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);
9304+
theEmitter->emitIns_R_R_R_I(INS_vminmaxpd, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0);
9305+
9306+
// VCVT[,T]PS2I[,U]BS
9307+
theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_16BYTE, REG_XMM0, REG_XMM1);
9308+
theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_32BYTE, REG_XMM0, REG_XMM1);
9309+
theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_32BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_ru);
9310+
theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_64BYTE, REG_XMM0, REG_XMM1);
9311+
theEmitter->emitIns_R_R(INS_vcvtps2ibs, EA_64BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_ru);
9312+
9313+
theEmitter->emitIns_R_R(INS_vcvtps2iubs, EA_16BYTE, REG_XMM0, REG_XMM1);
9314+
theEmitter->emitIns_R_R(INS_vcvtps2iubs, EA_32BYTE, REG_XMM0, REG_XMM1);
9315+
theEmitter->emitIns_R_R(INS_vcvtps2iubs, EA_32BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_rz);
9316+
theEmitter->emitIns_R_R(INS_vcvtps2iubs, EA_64BYTE, REG_XMM0, REG_XMM1);
9317+
theEmitter->emitIns_R_R(INS_vcvtps2iubs, EA_64BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_rz);
9318+
9319+
theEmitter->emitIns_R_R(INS_vcvttps2ibs, EA_16BYTE, REG_XMM0, REG_XMM1);
9320+
theEmitter->emitIns_R_R(INS_vcvttps2ibs, EA_32BYTE, REG_XMM0, REG_XMM1);
9321+
theEmitter->emitIns_R_R(INS_vcvttps2ibs, EA_32BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_eb_er_rd);
9322+
theEmitter->emitIns_R_R(INS_vcvttps2ibs, EA_64BYTE, REG_XMM0, REG_XMM1);
9323+
9324+
theEmitter->emitIns_R_R(INS_vcvttps2iubs, EA_16BYTE, REG_XMM0, REG_XMM1);
9325+
theEmitter->emitIns_R_R(INS_vcvttps2iubs, EA_32BYTE, REG_XMM0, REG_XMM1);
9326+
theEmitter->emitIns_R_R(INS_vcvttps2iubs, EA_32BYTE, REG_XMM0, REG_XMM1, INS_OPTS_EVEX_er_ru);
9327+
theEmitter->emitIns_R_R(INS_vcvttps2iubs, EA_64BYTE, REG_XMM0, REG_XMM1);
9328+
9329+
// VPDPW[SU,US,UU]D[,S]
9330+
theEmitter->emitIns_R_R_R(INS_vpdpwsud, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9331+
theEmitter->emitIns_R_R_R(INS_vpdpwsud, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9332+
theEmitter->emitIns_R_R_R(INS_vpdpwsud, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9333+
theEmitter->emitIns_R_R_R(INS_vpdpwsuds, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9334+
theEmitter->emitIns_R_R_R(INS_vpdpwsuds, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9335+
theEmitter->emitIns_R_R_R(INS_vpdpwsuds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9336+
9337+
theEmitter->emitIns_R_R_R(INS_vpdpwusd, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9338+
theEmitter->emitIns_R_R_R(INS_vpdpwusd, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9339+
theEmitter->emitIns_R_R_R(INS_vpdpwusd, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9340+
theEmitter->emitIns_R_R_R(INS_vpdpwusds, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9341+
theEmitter->emitIns_R_R_R(INS_vpdpwusds, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9342+
theEmitter->emitIns_R_R_R(INS_vpdpwusds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9343+
9344+
theEmitter->emitIns_R_R_R(INS_vpdpwuud, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9345+
theEmitter->emitIns_R_R_R(INS_vpdpwuud, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9346+
theEmitter->emitIns_R_R_R(INS_vpdpwuud, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9347+
theEmitter->emitIns_R_R_R(INS_vpdpwuuds, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9348+
theEmitter->emitIns_R_R_R(INS_vpdpwuuds, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9349+
theEmitter->emitIns_R_R_R(INS_vpdpwuuds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9350+
9351+
// VPDPB[SU,UU,SS]D[,S]
9352+
theEmitter->emitIns_R_R_R(INS_vpdpbssd, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9353+
theEmitter->emitIns_R_R_R(INS_vpdpbssd, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9354+
theEmitter->emitIns_R_R_R(INS_vpdpbssd, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9355+
theEmitter->emitIns_R_R_R(INS_vpdpbssds, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9356+
theEmitter->emitIns_R_R_R(INS_vpdpbssds, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9357+
theEmitter->emitIns_R_R_R(INS_vpdpbssds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9358+
9359+
theEmitter->emitIns_R_R_R(INS_vpdpbsud, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9360+
theEmitter->emitIns_R_R_R(INS_vpdpbsud, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9361+
theEmitter->emitIns_R_R_R(INS_vpdpbsud, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9362+
theEmitter->emitIns_R_R_R(INS_vpdpbsuds, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9363+
theEmitter->emitIns_R_R_R(INS_vpdpbsuds, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9364+
theEmitter->emitIns_R_R_R(INS_vpdpbsuds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9365+
9366+
theEmitter->emitIns_R_R_R(INS_vpdpbuud, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9367+
theEmitter->emitIns_R_R_R(INS_vpdpbuud, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9368+
theEmitter->emitIns_R_R_R(INS_vpdpbuud, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9369+
theEmitter->emitIns_R_R_R(INS_vpdpbuuds, EA_16BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9370+
theEmitter->emitIns_R_R_R(INS_vpdpbuuds, EA_32BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9371+
theEmitter->emitIns_R_R_R(INS_vpdpbuuds, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2);
9372+
9373+
// VMPSADBW
9374+
theEmitter->emitIns_R_R_R_I(INS_vmpsadbw, EA_64BYTE, REG_XMM0, REG_XMM1, REG_XMM2, 0); // zmm
9375+
9376+
// VCOMXSD
9377+
theEmitter->emitIns_R_R(INS_vcomxsd, EA_16BYTE, REG_XMM0, REG_XMM1);
9378+
9379+
// VCOMXSS
9380+
theEmitter->emitIns_R_R(INS_vcomxss, EA_16BYTE, REG_XMM0, REG_XMM1);
9381+
9382+
// VUCOMXSD
9383+
theEmitter->emitIns_R_R(INS_vucomxsd, EA_16BYTE, REG_XMM0, REG_XMM1);
9384+
9385+
// VUCOMXSS
9386+
theEmitter->emitIns_R_R(INS_vucomxss, EA_16BYTE, REG_XMM0, REG_XMM1);
9387+
9388+
// VMOVD
9389+
theEmitter->emitIns_R_R(INS_vmovd, EA_16BYTE, REG_XMM0, REG_XMM1);
9390+
9391+
// VMOVW
9392+
theEmitter->emitIns_R_R(INS_vmovw, EA_16BYTE, REG_XMM0, REG_XMM1);
9393+
}
9394+
92429395
#endif // defined(DEBUG) && defined(TARGET_AMD64)
92439396

92449397
#ifdef PROFILING_SUPPORTED

‎src/coreclr/jit/emit.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1607,36 +1607,36 @@ class emitter
16071607

16081608
bool idIsBound() const
16091609
{
1610-
assert(!IsAvx512OrPriorInstruction(_idIns));
1610+
assert(!IsSimdInstruction(_idIns));
16111611
return _idBound != 0;
16121612
}
16131613
void idSetIsBound()
16141614
{
1615-
assert(!IsAvx512OrPriorInstruction(_idIns));
1615+
assert(!IsSimdInstruction(_idIns));
16161616
_idBound = 1;
16171617
}
16181618

16191619
#ifndef TARGET_ARMARCH
16201620
bool idIsCallRegPtr() const
16211621
{
1622-
assert(!IsAvx512OrPriorInstruction(_idIns));
1622+
assert(!IsSimdInstruction(_idIns));
16231623
return _idCallRegPtr != 0;
16241624
}
16251625
void idSetIsCallRegPtr()
16261626
{
1627-
assert(!IsAvx512OrPriorInstruction(_idIns));
1627+
assert(!IsSimdInstruction(_idIns));
16281628
_idCallRegPtr = 1;
16291629
}
16301630
#endif // !TARGET_ARMARCH
16311631

16321632
bool idIsTlsGD() const
16331633
{
1634-
assert(!IsAvx512OrPriorInstruction(_idIns));
1634+
assert(!IsSimdInstruction(_idIns));
16351635
return _idTlsGD != 0;
16361636
}
16371637
void idSetTlsGD()
16381638
{
1639-
assert(!IsAvx512OrPriorInstruction(_idIns));
1639+
assert(!IsSimdInstruction(_idIns));
16401640
_idTlsGD = 1;
16411641
}
16421642

@@ -1645,12 +1645,12 @@ class emitter
16451645
// code, it is not necessary to generate GC info for a call so labeled.
16461646
bool idIsNoGC() const
16471647
{
1648-
assert(!IsAvx512OrPriorInstruction(_idIns));
1648+
assert(!IsSimdInstruction(_idIns));
16491649
return _idNoGC != 0;
16501650
}
16511651
void idSetIsNoGC(bool val)
16521652
{
1653-
assert(!IsAvx512OrPriorInstruction(_idIns));
1653+
assert(!IsSimdInstruction(_idIns));
16541654
_idNoGC = val;
16551655
}
16561656

@@ -1703,7 +1703,7 @@ class emitter
17031703

17041704
unsigned idGetEvexAaaContext() const
17051705
{
1706-
assert(IsAvx512OrPriorInstruction(_idIns));
1706+
assert(IsSimdInstruction(_idIns));
17071707
return _idEvexAaaContext;
17081708
}
17091709

@@ -1719,7 +1719,7 @@ class emitter
17191719

17201720
bool idIsEvexZContextSet() const
17211721
{
1722-
assert(IsAvx512OrPriorInstruction(_idIns));
1722+
assert(IsSimdInstruction(_idIns));
17231723
return _idEvexZContext != 0;
17241724
}
17251725

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