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fky2015fky2015
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update mycpu_top to idcached
1 parent 437dfa7 commit cc93a2f

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-163
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+140
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‎src/mycpu_top.v

+140-163
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ module mycpu_top(
44
input
55
wire aclk,
66
wire aresetn,
7-
wire[5:0] int_i,
7+
wire[5:0] ext_int,
88

99

1010
// write address channel signals
@@ -17,7 +17,7 @@ module mycpu_top(
1717
wire[1:0] awlock,
1818
wire[3:0] awcache,
1919
wire[2:0] awprot,
20-
output wire awvalid,
20+
output wire awvalid,
2121
input
2222
wire awready,
2323

@@ -34,7 +34,7 @@ module mycpu_top(
3434
input
3535
wire[3:0] bid,
3636
wire[1:0] bresp,
37-
input wire bvalid,
37+
input wire bvalid,
3838
output
3939
wire bready,
4040

@@ -43,25 +43,25 @@ module mycpu_top(
4343
output
4444
wire[3:0] arid,
4545
wire[31:0] araddr,
46-
wire[3:0] arlen,
46+
wire[3:0] arlen,
4747
wire[2:0] arsize,
4848
wire[1:0] arburst,
4949
wire[1:0] arlock,
5050
wire[3:0] arcache,
5151
wire[2:0] arprot,
52-
output wire arvalid,
52+
output wire arvalid,
5353
input
5454
wire arready,
5555

5656
// read data channel signals
5757
input
58-
wire[3:0] rid,
59-
wire[31:0] rdata,
60-
wire[1:0] rresp,
61-
input wire rlast,
62-
wire rvalid,
58+
wire[3:0] rid,
59+
wire[31:0] rdata,
60+
wire[1:0] rresp,
61+
input wire rlast,
62+
wire rvalid,
6363
output
64-
wire rready,
64+
wire rready,
6565

6666

6767
// port for debug
@@ -91,7 +91,7 @@ wire[`RegBus] current_inst_address;
9191
wire flush;
9292
wire mem_addr_read_ready;
9393
wire if_id_full;
94-
wire[1:0] axi_read_state;
94+
wire[1:0] axi_read_state;
9595

9696

9797

@@ -226,14 +226,14 @@ axi_crossbar_0 axi_crossbar_0_merge (
226226

227227

228228
// memory write
229-
wire[3:0] mw_awid;
230-
wire[31:0] mw_awaddr;
231-
wire[3:0] mw_awlen;
232-
wire[2:0] mw_awsize;
233-
wire[1:0] mw_awburst;
234-
wire[1:0] mw_awlock;
235-
wire[3:0] mw_awcache;
236-
wire[2:0] mw_awprot;
229+
wire[3:0] mw_awid;
230+
wire[31:0] mw_awaddr;
231+
wire[3:0] mw_awlen;
232+
wire[2:0] mw_awsize;
233+
wire[1:0] mw_awburst;
234+
wire[1:0] mw_awlock;
235+
wire[3:0] mw_awcache;
236+
wire[2:0] mw_awprot;
237237
wire mw_awvalid;
238238
wire mw_awready;
239239
wire[3:0] mw_wid;
@@ -248,40 +248,40 @@ wire mw_bvalid;
248248
wire mw_bready;
249249

250250
wire[3:0] mr_arid;
251-
wire[31:0] mr_araddr;
251+
wire[31:0] mr_araddr;
252252
wire[3:0] mr_arlen;
253253
wire[2:0] mr_arsize;
254254
wire[1:0] mr_arburst;
255255
wire[1:0] mr_arlock;
256256
wire[3:0] mr_arcache;
257257
wire[2:0] mr_arprot;
258-
wire mr_arvalid;
259-
wire mr_arready;
260-
wire mr_flush;
261-
wire[3:0] mr_rid;
262-
wire[31:0] mr_rdata;
263-
wire[1:0] mr_rresp;
264-
wire mr_rlast;
265-
wire mr_rvalid;
266-
wire mr_rready;
258+
wire mr_arvalid;
259+
wire mr_arready;
260+
wire mr_flush;
261+
wire[3:0] mr_rid;
262+
wire[31:0] mr_rdata;
263+
wire[1:0] mr_rresp;
264+
wire mr_rlast;
265+
wire mr_rvalid;
266+
wire mr_rready;
267267

268268
wire[3:0] ir_arid;
269-
wire[31:0] ir_araddr;
269+
wire[31:0] ir_araddr;
270270
wire[3:0] ir_arlen;
271271
wire[2:0] ir_arsize;
272272
wire[1:0] ir_arburst;
273273
wire[1:0] ir_arlock;
274274
wire[3:0] ir_arcache;
275275
wire[2:0] ir_arprot;
276-
wire ir_arvalid;
277-
wire ir_arready;
278-
wire ir_flush;
279-
wire[3:0] ir_rid;
280-
wire[31:0] ir_rdata;
281-
wire[1:0] ir_rresp;
282-
wire ir_rlast;
283-
wire ir_rvalid;
284-
wire ir_rready;
276+
wire ir_arvalid;
277+
wire ir_arready;
278+
wire ir_flush;
279+
wire[3:0] ir_rid;
280+
wire[31:0] ir_rdata;
281+
wire[1:0] ir_rresp;
282+
wire ir_rlast;
283+
wire ir_rvalid;
284+
wire ir_rready;
285285

286286
assign s_axi_awid = {4'b0, mw_awid};
287287
assign s_axi_awaddr = {32'b0, mw_awaddr};
@@ -331,117 +331,106 @@ wire[`RegBus] data_wdata;
331331
wire data_addr_ok;
332332
wire data_data_ok;
333333
wire[`RegBus] data_rdata;
334-
wire data_data_ok_read;
335-
wire data_data_ok_write;
336-
337-
// mem write
338-
axi_write_adapter axi_write_adapter0(
339-
.clk(aclk), .reset(aresetn),
340-
341-
.awid(mw_awid),
342-
.awaddr(mw_awaddr),
343-
.awlen(mw_awlen),
344-
.awsize(mw_awsize),
345-
.awburst(mw_awburst),
346-
.awlock(mw_awlock),
347-
.awcache(mw_awcache),
348-
.awprot(mw_awprot),
349-
.awvalid(mw_awvalid),
350-
.awready(mw_awready),
351-
.wid(mw_wid),
352-
.wdata(mw_wdata),
353-
.wstrb(mw_wstrb),
354-
.wlast(mw_wlast),
355-
.wvalid(mw_wvalid),
356-
.wready(mw_wready),
357-
.bid(mw_bid),
358-
.bresp(mw_bresp),
359-
.bvalid(mw_bvalid),
360-
.bready(mw_bready),
361-
362-
.data(data_wdata),
363-
.we((data_req == 1'b1 && data_wr == 1'b1)?1'b1: 1'b0),
364-
.address(data_addr),
365-
.select(data_select),
366-
.mem_write_done(data_data_ok_write)
367-
);
368-
369-
wire data_addr_ok_write;
370-
assign data_addr_ok_write = data_data_ok_write;
371-
372-
wire data_addr_ok_read;
373-
374-
// data read
375-
new_axi_read_adapter new_axi_read_adapter_mem(
376-
.clk(aclk),
377-
.reset(aresetn),
378-
.flush(flush),
379-
380-
.arid(mr_arid),
381-
.araddr(mr_araddr),
382-
.arlen(mr_arlen),
383-
.arsize(mr_arsize),
384-
.arburst(mr_arburst),
385-
.arlock(mr_arlock),
386-
.arcache(mr_arcache),
387-
.arprot(mr_arprot),
388-
.arvalid(mr_arvalid),
389-
.arready(mr_arready),
390-
.rid(mr_rid),
391-
.rdata(mr_rdata),
392-
.rresp(mr_rresp),
393-
.rvalid(mr_rvalid),
394-
.rready(mr_rready),
395-
.rlast(mr_rlast),
396-
397-
.address(data_addr),
398-
.address_valid((data_req == 1'b1 && data_wr == 1'b0 )? 1'b1: 1'b0),
399-
.address_read_ready(data_addr_ok_read),
400-
401-
.data_valid(data_data_ok_read),
402-
.data(data_rdata),
403-
.data_address()
404-
);
405334

406-
// inst read
407-
new_axi_read_adapter new_axi_read_adapter_inst(
408-
.clk(aclk),
409-
.reset(aresetn),
410-
.flush(flush),
411-
412-
.arid(ir_arid),
413-
.araddr(ir_araddr),
414-
.arlen(ir_arlen),
415-
.arsize(ir_arsize),
416-
.arburst(ir_arburst),
417-
.arlock(ir_arlock),
418-
.arcache(ir_arcache),
419-
.arprot(ir_arprot),
420-
.arvalid(ir_arvalid),
421-
.arready(ir_arready),
422-
.rid(ir_rid),
423-
.rdata(ir_rdata),
424-
.rresp(ir_rresp),
425-
.rvalid(ir_rvalid),
426-
.rready(ir_rready),
427-
.rlast(ir_rlast),
428-
429-
430-
.address(rom_addr),
431-
.address_valid(rom_re),
432-
.address_read_ready(pc_ready),
433-
434-
.data_valid(inst_valid),
435-
.data(rom_data),
436335

437-
.data_address(current_inst_address)
438-
);
336+
// data r/w
337+
dcache dcache_0(
338+
.clk(aclk),
339+
.rstn(aresetn),
340+
341+
342+
// AXI
343+
.arid(mr_arid),
344+
.araddr(mr_araddr),
345+
.arlen(mr_arlen),
346+
.arsize(mr_arsize),
347+
.arburst(mr_arburst),
348+
.arlock(mr_arlock),
349+
.arcache(mr_arcache),
350+
.arprot(mr_arprot),
351+
.arvalid(mr_arvalid),
352+
.arready(mr_arready),
353+
354+
.rid(mr_rid),
355+
.rdata(mr_rdata),
356+
.rresp(mr_rresp),
357+
.rvalid(mr_rvalid),
358+
.rready(mr_rready),
359+
.rlast(mr_rlast),
360+
361+
.awid(mw_awid),
362+
.awaddr(mw_awaddr),
363+
.awlen(mw_awlen),
364+
.awsize(mw_awsize),
365+
.awburst(mw_awburst),
366+
.awlock(mw_awlock),
367+
.awcache(mw_awcache),
368+
.awprot(mw_awprot),
369+
.awvalid(mw_awvalid),
370+
.awready(mw_awready),
371+
372+
.wid(mw_wid),
373+
.wdata(mw_wdata),
374+
.wstrb(mw_wstrb),
375+
.wlast(mw_wlast),
376+
.wvalid(mw_wvalid),
377+
.wready(mw_wready),
378+
379+
.bid(mw_bid),
380+
.bresp(mw_bresp),
381+
.bvalid(mw_bvalid),
382+
.bready(mw_bready),
383+
384+
385+
// CPU SRAM like
386+
.data_req(data_req),
387+
.data_wr(data_wr),
388+
389+
.data_addr_ok(data_addr_ok),
390+
.data_addr(data_addr),
391+
392+
.data_data_ok(data_data_ok),
393+
.data_rdata(data_rdata),
394+
395+
.data_sel(data_select),
396+
.data_wdata(data_wdata)
397+
398+
// .data_cache(1'b0)
399+
);
439400

440401

441-
// data write
442-
443-
444-
// data read
402+
// inst read
403+
inst_cache inst_cache_0(
404+
.clk(aclk),
405+
.rstn(aresetn),
406+
.flush(flush),
407+
408+
.arid(ir_arid),
409+
.araddr(ir_araddr),
410+
.arlen(ir_arlen),
411+
.arsize(ir_arsize),
412+
.arburst(ir_arburst),
413+
.arlock(ir_arlock),
414+
.arcache(ir_arcache),
415+
.arprot(ir_arprot),
416+
.arvalid(ir_arvalid),
417+
.arready(ir_arready),
418+
.rid(ir_rid),
419+
.rdata(ir_rdata),
420+
.rresp(ir_rresp),
421+
.rvalid(ir_rvalid),
422+
.rready(ir_rready),
423+
.rlast(ir_rlast),
424+
425+
.inst_req(rom_re), // cpu::rom_ce_o == read_adapter::address_valid
426+
.inst_addr_ready(pc_ready), // cpu::pc_ready == read_adapter::address_read_ready
427+
.inst_addr(rom_addr),
428+
.inst_addr_out(current_inst_address),
429+
.inst_rdata(rom_data),
430+
.inst_data_ok(inst_valid)
431+
432+
// .inst_cache(1'b0)
433+
);
445434

446435

447436
openmips openmips0(
@@ -462,24 +451,12 @@ openmips openmips0(
462451
.data_select(data_select),
463452
.data_addr(data_addr),
464453
.data_wdata(data_wdata),
465-
.data_addr_ok( (data_addr_ok_read || data_addr_ok_write)),
466-
.data_data_ok((data_data_ok_read || data_data_ok_write)),
454+
.data_addr_ok(data_addr_ok),
455+
.data_data_ok(data_data_ok),
467456
.data_rdata(data_rdata),
468-
// .mem_addr_read_ready(mem_addr_read_ready),
469-
470-
// .full(if_id_full),
471-
// .mem_data_ready(mem_data_ready),
472-
// .ram_data_i(ram_data_i),
473-
// .ram_addr_o(ram_addr),
474-
// .ram_data_o(ram_data_o),
475-
// .ram_we_o(ram_we),
476-
// .ram_sel_o(ram_sel),
477-
// .ram_re_o(ram_re),
478-
// .ram_write_ready(ram_write_ready),
479-
// .ram_read_valid(ram_read_ready),
480-
.int_i(int_i),
457+
458+
.int_i(ext_int),
481459
.timer_int_o(),
482-
// .ram_ce_o(),
483460

484461
.debug_wb_pc(debug_wb_pc),
485462
.debug_wb_rf_wen(debug_wb_rf_wen),

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