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biemsterbiemster
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add CH573 as well
1 parent 507eee5 commit 839e8d1

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6 files changed

+378
-50
lines changed

6 files changed

+378
-50
lines changed

‎ch32fun/ch57xhw.h

Lines changed: 127 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -22,22 +22,34 @@ typedef enum IRQn
2222
Software_IRQn = 14, /* 14 software Interrupt */
2323

2424
/****** RISC-V specific Interrupt Numbers *********************************************************/
25+
TMR0_IRQn = 16, /* TMR0 */
2526
GPIOA_IRQn = 17, /* GPIOA */
26-
SPI_IRQn = 19, /* SPI */
27+
GPIOB_IRQn = 18, /* GPIOB */
28+
SPI0_IRQn = 19, /* SPI0 */
2729
BB_IRQn = 20, /* BLEB */
2830
LLE_IRQn = 21, /* BLEL */
2931
USB_IRQn = 22, /* USB */
30-
TMR_IRQn = 24, /* TMR */
31-
UART_IRQn = 27, /* UART */
32+
TMR1_IRQn = 24, /* TMR1 */
33+
TMR2_IRQn = 25, /* TMR2 */
34+
UART0_IRQn = 26, /* UART0 */
35+
UART1_IRQn = 27, /* UART1 */
3236
RTC_IRQn = 28, /* RTC */
33-
CMP_IRQn = 29, /* CMP */
37+
ADC_IRQn = 29, /* CMP */
3438
I2C_IRQn = 30, /* I2C */
3539
PWMX_IRQn = 31, /* PWMX */
36-
KEYSCAN_IRQn = 33, /* KEYSCAN */
37-
ENCODER_IRQn = 34, /* ENCODER */
40+
TMR3_IRQn = 32, /* TMR3 */
41+
UART2_IRQn = 33, /* UART2 / KEYSCAN */
42+
UART3_IRQn = 34, /* UART3 / ENCODER */
3843
WDOG_BAT_IRQn = 35, /* WDOG_BAT */
3944
} IRQn_Type;
4045

46+
#define TMR_IRQn TMR1_IRQn
47+
#define SPI_IRQn SPI0_IRQn
48+
#define UART_IRQn UART1_IRQn
49+
#define CMP_IRQn ADC_IRQn
50+
#define KEYSCAN_IRQn UART2_IRQn
51+
#define ENCODER_IRQn UART3_IRQn
52+
4153
#define BASE_VECTOR "\n\
4254
.balign 2\n\
4355
.option push;\n\
@@ -59,46 +71,59 @@ typedef enum IRQn
5971
.word SW_Handler /* SW Handler */\n\
6072
.word 0\n\
6173
/* External Interrupts */\n\
62-
.word 0 /* 16 */\n\
74+
.word TMR0_IRQHandler /* 16: TMR0 */\n\
6375
.word GPIOA_IRQHandler /* GPIOA */\n\
64-
.word 0 \n\
65-
.word SPI_IRQHandler /* SPI */\n\
76+
.word GPIOB_IRQHandler /* GPIOB */\n\
77+
.word SPI0_IRQHandler /* SPI0 */\n\
6678
.word BB_IRQHandler /* BLEB */\n\
6779
.word LLE_IRQHandler /* BLEL */\n\
6880
.word USB_IRQHandler /* USB */\n\
6981
.word 0 \n\
70-
.word TMR_IRQHandler /* TMR */\n\
71-
.word 0 \n\
72-
.word 0 \n\
73-
.word UART_IRQHandler /* UART */\n\
82+
.word TMR1_IRQHandler /* TMR1 */\n\
83+
.word TMR2_IRQHandler /* TMR2 */\n\
84+
.word UART0_IRQHandler /* UART0 */\n\
85+
.word UART1_IRQHandler /* UART1 */\n\
7486
.word RTC_IRQHandler /* RTC */\n\
75-
.word CMP_IRQHandler /* CMP */\n\
87+
.word ADC_IRQHandler /* ADC */\n\
7688
.word I2C_IRQHandler /* I2C */\n\
7789
.word PWMX_IRQHandler /* PWMX */\n\
78-
.word 0 \n\
79-
.word KEYSCAN_IRQHandler /* KEYSCAN */\n\
80-
.word ENCODER_IRQHandler /* ENCODER */\n\
90+
.word TMR3_IRQHandler /* TMR3 */\n\
91+
.word UART2_IRQHandler /* UART2 / KEYSCAN */\n\
92+
.word UART3_IRQHandler /* UART3 / ENCODER */\n\
8193
.word WDOG_BAT_IRQHandler /* WDOG_BAT */\n"
8294

95+
// ch570/2 has slightly different interrupts
96+
#define TMR_IRQHandler TMR1_IRQHandler
97+
#define SPI_IRQHandler SPI0_IRQHandler
98+
#define UART_IRQHandler UART1_IRQHandler
99+
#define CMP_IRQHandler ADC_IRQHandler
100+
#define KEYSCAN_IRQHandler UART2_IRQHandler
101+
#define ENCODER_IRQHandler UART3_IRQHandler
83102
#define DEFAULT_INTERRUPT_VECTOR_CONTENTS BASE_VECTOR "\n.option pop;\n"
84103

85104
/* memory mapped structure for SysTick */
86-
typedef struct
105+
typedef struct __attribute__((packed))
87106
{
88-
__IO uint32_t CTLR;
89-
__IO uint32_t SR;
90-
union
91-
{
92-
__IO uint32_t CNT;
93-
__IO uint32_t CNTL;
94-
};
95-
uint8_t RESERVED[4];
96-
union
107+
__IO uint32_t CTLR;
108+
#if MCU_PACKAGE == 3
109+
__IO uint64_t CNT;
110+
__IO uint64_t CMP;
111+
__IO uint32_t CNTFG;
112+
#else
113+
__IO uint32_t SR;
114+
union
115+
{
116+
__IO uint32_t CNT;
117+
__IO uint32_t CNTL;
118+
};
119+
uint8_t RESERVED[4];
120+
union
97121
{
98122
__IO uint32_t CMP;
99123
__IO uint32_t CMPL;
100124
};
101125
uint8_t RESERVED0[4];
126+
#endif
102127
} SysTick_Type;
103128

104129
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
@@ -107,7 +132,7 @@ typedef struct
107132
__I uint32_t ISR[8]; // 0
108133
__I uint32_t IPR[8]; // 20H
109134
__IO uint32_t ITHRESDR; // 40H
110-
uint8_t RESERVED[8]; // 44H
135+
uint8_t RESERVED[4]; // 44H
111136
__O uint32_t CFGR; // 48H
112137
__I uint32_t GISR; // 4CH
113138
__IO uint8_t VTFIDR[4]; // 50H
@@ -142,8 +167,8 @@ typedef struct
142167
#define PFIC ((PFIC_Type *) PFIC_BASE)
143168
#define NVIC PFIC
144169
#define NVIC_KEY1 ((uint32_t)0xFA050000)
145-
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
146-
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
170+
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
171+
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
147172

148173
#define SysTick ((SysTick_Type *) SysTick_BASE)
149174
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFFFFFFFFFFF)
@@ -158,6 +183,26 @@ typedef struct
158183

159184
typedef enum
160185
{
186+
#if MCU_PACKAGE == 3
187+
CLK_SOURCE_LSI = 0x00,
188+
CLK_SOURCE_LSE,
189+
190+
CLK_SOURCE_HSE_8MHz = 0x24,
191+
CLK_SOURCE_HSE_6_4MHz = 0x25,
192+
CLK_SOURCE_HSE_4MHz = 0x28,
193+
CLK_SOURCE_HSE_2MHz = (0x20 | 16),
194+
CLK_SOURCE_HSE_1MHz = (0x20 | 0),
195+
196+
CLK_SOURCE_PLL_60MHz = 0x48,
197+
CLK_SOURCE_PLL_48MHz = (0x40 | 10),
198+
CLK_SOURCE_PLL_40MHz = (0x40 | 12),
199+
CLK_SOURCE_PLL_36_9MHz = (0x40 | 13),
200+
CLK_SOURCE_PLL_32MHz = (0x40 | 15),
201+
CLK_SOURCE_PLL_30MHz = (0x40 | 16),
202+
CLK_SOURCE_PLL_24MHz = (0x40 | 20),
203+
CLK_SOURCE_PLL_20MHz = (0x40 | 24),
204+
CLK_SOURCE_PLL_15MHz = (0x40 | 0),
205+
#else
161206
CLK_SOURCE_LSI = 0xC0,
162207

163208
CLK_SOURCE_HSE_16MHz = (0x02),
@@ -167,15 +212,16 @@ typedef enum
167212
CLK_SOURCE_HSE_2MHz = (0x10),
168213
CLK_SOURCE_HSE_1MHz = (0x0),
169214

170-
CLK_SOURCE_HSE_PLL_100MHz = (0x40 | 6),
171-
CLK_SOURCE_HSE_PLL_75MHz = (0x40 | 8),
172-
CLK_SOURCE_HSE_PLL_60MHz = (0x40 | 10),
173-
CLK_SOURCE_HSE_PLL_50MHz = (0x40 | 12),
174-
CLK_SOURCE_HSE_PLL_40MHz = (0x40 | 15),
175-
CLK_SOURCE_HSE_PLL_30MHz = (0x40 | 20),
176-
CLK_SOURCE_HSE_PLL_25MHz = (0x40 | 24),
177-
CLK_SOURCE_HSE_PLL_24MHz = (0x40 | 25),
178-
CLK_SOURCE_HSE_PLL_20MHz = (0x40 | 30),
215+
CLK_SOURCE_PLL_100MHz = (0x40 | 6),
216+
CLK_SOURCE_PLL_75MHz = (0x40 | 8),
217+
CLK_SOURCE_PLL_60MHz = (0x40 | 10),
218+
CLK_SOURCE_PLL_50MHz = (0x40 | 12),
219+
CLK_SOURCE_PLL_40MHz = (0x40 | 15),
220+
CLK_SOURCE_PLL_30MHz = (0x40 | 20),
221+
CLK_SOURCE_PLL_25MHz = (0x40 | 24),
222+
CLK_SOURCE_PLL_24MHz = (0x40 | 25),
223+
CLK_SOURCE_PLL_20MHz = (0x40 | 30),
224+
#endif
179225
} SYS_CLKTypeDef;
180226

181227
// For debug writing to the debug interface.
@@ -188,6 +234,8 @@ typedef enum
188234
#define R8_CLK_SYS_CFG (*((vu8*)0x40001008)) // RWA, system clock configuration, SAM
189235
#define RB_CLK_SYS_MOD 0xC0 // RWA, system clock source mode: 00/10=divided from 32MHz, 01=divided from PLL-600MHz,11=directly from LSI
190236
#define RB_CLK_PLL_DIV 0x1F // RWA, output clock divider from PLL or CK32M
237+
#define RB_TX_32M_PWR_EN 0x40000 // RWA, extern 32MHz HSE power contorl
238+
#define RB_PLL_PWR_EN 0x100000 // RWA, PLL power control
191239
#define R8_HFCK_PWR_CTRL (*((vu8*)0x4000100A)) // RWA, power configuration for system high clock, SAM
192240
#define RB_CLK_PLL_PON 0x10 // RWA, PLL power control
193241
#define RB_CLK_XT32M_KEEP 0x08 // RWA, RWA, disable auto closing when in halt mode
@@ -232,6 +280,15 @@ typedef enum
232280
#define R32_PA_PD_DRV (*((vu32*)0x400010B4)) // RW, PA pulldown for input or PA driving capability for output
233281
#define R32_PA_SET (*((vu32*)0x400010B8)) // RW, PA set high for output ,1=set output high,0=IDLE
234282

283+
/* GPIO PB register */
284+
#define R32_PB_DIR (*((vu32*)0x400010C0)) // RW, GPIO PB I/O direction: 0=in, 1=out
285+
#define R32_PB_PIN (*((vu32*)0x400010C4)) // RO, GPIO PB input
286+
#define R32_PB_OUT (*((vu32*)0x400010C8)) // RW, GPIO PB output
287+
#define R32_PB_CLR (*((vu32*)0x400010CC)) // WZ, GPIO PB clear output: 0=keep, 1=clear
288+
#define R32_PB_PU (*((vu32*)0x400010D0)) // RW, GPIO PB pullup resistance enable
289+
#define R32_PB_PD_DRV (*((vu32*)0x400010D4)) // RW, PB pulldown for input or PB driving capability for output
290+
#define R32_PB_SET (*((vu32*)0x400010D8)) // RW, PB set high for output ,1=set output high,0=IDLE
291+
235292
#define PA0 (0x00000001) /*!< Pin 0 selected */
236293
#define PA1 (0x00000002) /*!< Pin 1 selected */
237294
#define PA2 (0x00000004) /*!< Pin 2 selected */
@@ -244,7 +301,37 @@ typedef enum
244301
#define PA9 (0x00000200) /*!< Pin 9 selected */
245302
#define PA10 (0x00000400) /*!< Pin 10 selected */
246303
#define PA11 (0x00000800) /*!< Pin 11 selected */
247-
#define PA_All (0xFFFFFFFF) /*!< All pins selected */
304+
#define PA12 (0x00001000) /*!< Pin 12 selected */
305+
#define PA13 (0x00002000) /*!< Pin 13 selected */
306+
#define PA14 (0x00004000) /*!< Pin 14 selected */
307+
#define PA15 (0x00008000) /*!< Pin 15 selected */
308+
309+
#define PB (0x80000000) /* Bit mask to indicate bank B */
310+
#define PB0 (0x80000001) /*!< Pin 0 selected */
311+
#define PB1 (0x80000002) /*!< Pin 1 selected */
312+
#define PB2 (0x80000004) /*!< Pin 2 selected */
313+
#define PB3 (0x80000008) /*!< Pin 3 selected */
314+
#define PB4 (0x80000010) /*!< Pin 4 selected */
315+
#define PB5 (0x80000020) /*!< Pin 5 selected */
316+
#define PB6 (0x80000040) /*!< Pin 6 selected */
317+
#define PB7 (0x80000080) /*!< Pin 7 selected */
318+
#define PB8 (0x80000100) /*!< Pin 8 selected */
319+
#define PB9 (0x80000200) /*!< Pin 9 selected */
320+
#define PB10 (0x80000400) /*!< Pin 10 selected */
321+
#define PB11 (0x80000800) /*!< Pin 11 selected */
322+
#define PB12 (0x80001000) /*!< Pin 12 selected */
323+
#define PB13 (0x80002000) /*!< Pin 13 selected */
324+
#define PB14 (0x80004000) /*!< Pin 14 selected */
325+
#define PB15 (0x80008000) /*!< Pin 15 selected */
326+
#define PB16 (0x80010000) /*!< Pin 16 selected */
327+
#define PB17 (0x80020000) /*!< Pin 17 selected */
328+
#define PB18 (0x80040000) /*!< Pin 18 selected */
329+
#define PB19 (0x80080000) /*!< Pin 19 selected */
330+
#define PB20 (0x80100000) /*!< Pin 20 selected */
331+
#define PB21 (0x80200000) /*!< Pin 21 selected */
332+
#define PB22 (0x80400000) /*!< Pin 22 selected */
333+
#define PB23 (0x80800000) /*!< Pin 23 selected */
334+
#define P_All (0xFFFFFFFF) /*!< All pins selected */
248335

249336
typedef enum
250337
{

‎examples_ch57x/blink/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
all : flash
22

33
TARGET:=blink
4-
TARGET_MCU:=CH570
5-
TARGET_MCU_PACKAGE:=CH570E
4+
TARGET_MCU:=CH573
5+
TARGET_MCU_PACKAGE:=CH573F
66

77
include ../../ch32fun/ch32fun.mk
88

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