ql-qlf: k6n10f: QL_DSP2_MULT: pass down acc_fir

Co-authored-by: Maciej Kurc <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>

Author: lpawelcz

ql-qlf-plugin/ql-dsp-io-regs.cc

@@ -11,7 +11,8 @@ PRIVATE_NAMESPACE_BEGIN
 // ============================================================================
 
 const std::vector<std::string> ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"};
-const std::vector<std::string> ports2del_mult_add_acc = {"acc_fir", "dly_b"};
+const std::vector<std::string> ports2del_mult_acc = {"acc_fir", "dly_b"};
+const std::vector<std::string> ports2del_mult_add = {"dly_b"};
 const std::vector<std::string> ports2del_extension = {"saturate_enable", "shift_right", "round"};
 
 void ql_dsp_io_regs_pass(RTLIL::Module *module)
@@ -95,10 +96,21 @@ void ql_dsp_io_regs_pass(RTLIL::Module *module)
             if (del_clk)
                 ports2del.push_back("clk");
 
-            if (out_sel_i == 0 || out_sel_i == 4) {
+            switch (out_sel_i) {
+            case 0:
+            case 4:
                 ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end());
-            } else {
-                ports2del.insert(ports2del.end(), ports2del_mult_add_acc.begin(), ports2del_mult_add_acc.end());
+                break;
+            case 1:
+            case 5:
+                ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end());
+                break;
+            case 2:
+            case 3:
+            case 6:
+            case 7:
+                ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end());
+                break;
             }
 
             // Mark for deleton additional configuration ports

ql-qlf-plugin/qlf_k6n10f/dsp_sim.v

@@ -386,6 +386,7 @@ module QL_DSP2_MULTADD (
     input  wire        reset,
 
     input  wire [ 2:0] feedback,
+    input  wire [ 5:0] acc_fir,
     input  wire        load_acc,
     input  wire        unsigned_a,
     input  wire        unsigned_b,
@@ -413,6 +414,7 @@ module QL_DSP2_MULTADD (
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .acc_fir(acc_fir),
         .load_acc(load_acc),
 
         .unsigned_a(unsigned_a),
@@ -437,6 +439,7 @@ module QL_DSP2_MULTADD_REGIN (
     input  wire        reset,
 
     input  wire [ 2:0] feedback,
+    input  wire [ 5:0] acc_fir,
     input  wire        load_acc,
     input  wire        unsigned_a,
     input  wire        unsigned_b,
@@ -464,6 +467,7 @@ module QL_DSP2_MULTADD_REGIN (
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .acc_fir(acc_fir),
         .load_acc(load_acc),
 
         .unsigned_a(unsigned_a),
@@ -488,6 +492,7 @@ module QL_DSP2_MULTADD_REGOUT (
     input  wire        reset,
 
     input  wire [ 2:0] feedback,
+    input  wire [ 5:0] acc_fir,
     input  wire        load_acc,
     input  wire        unsigned_a,
     input  wire        unsigned_b,
@@ -515,6 +520,7 @@ module QL_DSP2_MULTADD_REGOUT (
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .acc_fir(acc_fir),
         .load_acc(load_acc),
 
         .unsigned_a(unsigned_a),
@@ -539,6 +545,7 @@ module QL_DSP2_MULTADD_REGIN_REGOUT (
     input  wire        reset,
 
     input  wire [ 2:0] feedback,
+    input  wire [ 5:0] acc_fir,
     input  wire        load_acc,
     input  wire        unsigned_a,
     input  wire        unsigned_b,
@@ -566,6 +573,7 @@ module QL_DSP2_MULTADD_REGIN_REGOUT (
         .f_mode(f_mode),
 
         .feedback(feedback),
+        .acc_fir(acc_fir),
         .load_acc(load_acc),
 
         .unsigned_a(unsigned_a),