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ql-qlf: k6n10f: DSP: pass down output_select and register_inputs configuration bits
Co-authored-by: Maciej Kurc <[email protected]> Signed-off-by: Pawel Czarnecki <[email protected]>
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‎ql-qlf-plugin/qlf_k6n10f/dsp_sim.v

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -232,8 +232,8 @@ module QL_DSP2_MULT ( // TODO: Name subject to change
232232
.unsigned_a(unsigned_a),
233233
.unsigned_b(unsigned_b),
234234

235-
.output_select(3'b0), // unregistered output: a * b (0)
236-
.register_inputs(1'b0) // unregistered inputs
235+
.output_select(output_select), // unregistered output: a * b (0)
236+
.register_inputs(register_inputs) // unregistered inputs
237237
);
238238
endmodule
239239

@@ -279,8 +279,8 @@ module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change
279279
.clk(clk),
280280
.reset(reset),
281281

282-
.output_select(3'b0), // unregistered output: a * b (0)
283-
.register_inputs(1'b1) // registered inputs
282+
.output_select(output_select), // unregistered output: a * b (0)
283+
.register_inputs(register_inputs) // registered inputs
284284
);
285285
endmodule
286286

@@ -325,8 +325,8 @@ module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change
325325
.clk(clk),
326326
.reset(reset),
327327

328-
.output_select(3'b100), // registered output: a * b (4)
329-
.register_inputs(1'b0) // unregistered inputs
328+
.output_select(output_select), // registered output: a * b (4)
329+
.register_inputs(register_inputs) // unregistered inputs
330330
);
331331
endmodule
332332

@@ -371,8 +371,8 @@ module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change
371371
.clk(clk),
372372
.reset(reset),
373373

374-
.output_select(3'b100), // registered output: a * b (4)
375-
.register_inputs(1'b1) // registered inputs
374+
.output_select(output_select), // registered output: a * b (4)
375+
.register_inputs(register_inputs) // registered inputs
376376
);
377377
endmodule
378378

@@ -420,9 +420,9 @@ module QL_DSP2_MULTADD (
420420

421421
.reset(reset),
422422

423-
.output_select(output_select), // unregistered output: ACCin (2, 3)
423+
.output_select(output_select), // unregistered output: ACCin (2, 3)
424424
.subtract(subtract),
425-
.register_inputs(1'b0) // unregistered inputs
425+
.register_inputs(register_inputs) // unregistered inputs
426426
);
427427
endmodule
428428

@@ -473,9 +473,9 @@ module QL_DSP2_MULTADD_REGIN (
473473
.clk(clk),
474474
.reset(reset),
475475

476-
.output_select(output_select), // unregistered output: ACCin (2, 3)
476+
.output_select(output_select), // unregistered output: ACCin (2, 3)
477477
.subtract(subtract),
478-
.register_inputs(1'b1) // registered inputs
478+
.register_inputs(register_inputs) // registered inputs
479479
);
480480
endmodule
481481

@@ -526,9 +526,9 @@ module QL_DSP2_MULTADD_REGOUT (
526526
.clk(clk),
527527
.reset(reset),
528528

529-
.output_select(output_select), // registered output: ACCin (6, 7)
529+
.output_select(output_select), // registered output: ACCin (6, 7)
530530
.subtract(subtract),
531-
.register_inputs(1'b0) // unregistered inputs
531+
.register_inputs(register_inputs) // unregistered inputs
532532
);
533533
endmodule
534534

@@ -579,9 +579,9 @@ module QL_DSP2_MULTADD_REGIN_REGOUT (
579579
.clk(clk),
580580
.reset(reset),
581581

582-
.output_select(output_select), // registered output: ACCin (6, 7)
582+
.output_select(output_select), // registered output: ACCin (6, 7)
583583
.subtract(subtract),
584-
.register_inputs(1'b1) // registered inputs
584+
.register_inputs(register_inputs) // registered inputs
585585
);
586586
endmodule
587587

@@ -630,9 +630,9 @@ module QL_DSP2_MULTACC (
630630
.clk(clk),
631631
.reset(reset),
632632

633-
.output_select(1'b1), // unregistered output: ACCout (1)
633+
.output_select(output_select), // unregistered output: ACCout (1)
634634
.subtract(subtract),
635-
.register_inputs(1'b0) // unregistered inputs
635+
.register_inputs(register_inputs) // unregistered inputs
636636
);
637637
endmodule
638638

@@ -681,9 +681,9 @@ module QL_DSP2_MULTACC_REGIN (
681681
.clk(clk),
682682
.reset(reset),
683683

684-
.output_select(1'b1), // unregistered output: ACCout (1)
684+
.output_select(output_select), // unregistered output: ACCout (1)
685685
.subtract(subtract),
686-
.register_inputs(1'b1) // registered inputs
686+
.register_inputs(register_inputs) // registered inputs
687687
);
688688
endmodule
689689

@@ -732,9 +732,9 @@ module QL_DSP2_MULTACC_REGOUT (
732732
.clk(clk),
733733
.reset(reset),
734734

735-
.output_select(3'b101), // registered output: ACCout (5)
735+
.output_select(output_select), // registered output: ACCout (5)
736736
.subtract(subtract),
737-
.register_inputs(1'b0) // unregistered inputs
737+
.register_inputs(register_inputs) // unregistered inputs
738738
);
739739
endmodule
740740

@@ -783,9 +783,9 @@ module QL_DSP2_MULTACC_REGIN_REGOUT (
783783
.clk(clk),
784784
.reset(reset),
785785

786-
.output_select(3'b101), // registered output: ACCout (5)
786+
.output_select(output_select), // registered output: ACCout (5)
787787
.subtract(subtract),
788-
.register_inputs(1'b1) // registered inputs
788+
.register_inputs(register_inputs) // registered inputs
789789
);
790790
endmodule
791791

@@ -1325,11 +1325,11 @@ module QL_DSP3_MULT ( // TODO: Name subject to change
13251325
localparam [19:0] COEFF_3 = MODE_BITS[79:60];
13261326

13271327
localparam [0:0] F_MODE = MODE_BITS[80];
1328-
localparam [2:0] OUTPUT_SELECT = 3'b0; // unregistered output: a * b (0)
1328+
localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0)
13291329
localparam [0:0] SATURATE_ENABLE = MODE_BITS[84];
13301330
localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85];
13311331
localparam [0:0] ROUND = MODE_BITS[91];
1332-
localparam [0:0] REGISTER_INPUTS = 1'b0; // unregistered inputs
1332+
localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs
13331333

13341334
QL_DSP3 #(
13351335
.MODE_BITS({
@@ -1382,11 +1382,11 @@ module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change
13821382
localparam [19:0] COEFF_3 = MODE_BITS[79:60];
13831383

13841384
localparam [0:0] F_MODE = MODE_BITS[80];
1385-
localparam [2:0] OUTPUT_SELECT = 3'b0; // unregistered output: a * b (0)
1385+
localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0)
13861386
localparam [0:0] SATURATE_ENABLE = MODE_BITS[84];
13871387
localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85];
13881388
localparam [0:0] ROUND = MODE_BITS[91];
1389-
localparam [0:0] REGISTER_INPUTS = 1'b1; // registered inputs
1389+
localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // registered inputs
13901390

13911391
QL_DSP3 #(
13921392
.MODE_BITS({
@@ -1439,11 +1439,11 @@ module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change
14391439
localparam [19:0] COEFF_3 = MODE_BITS[79:60];
14401440

14411441
localparam [0:0] F_MODE = MODE_BITS[80];
1442-
localparam [2:0] OUTPUT_SELECT = 3'b100; // registered output: a * b (4)
1442+
localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4)
14431443
localparam [0:0] SATURATE_ENABLE = MODE_BITS[84];
14441444
localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85];
14451445
localparam [0:0] ROUND = MODE_BITS[91];
1446-
localparam [0:0] REGISTER_INPUTS = 1'b0; // unregistered inputs
1446+
localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs
14471447

14481448
QL_DSP3 #(
14491449
.MODE_BITS({
@@ -1496,11 +1496,11 @@ module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change
14961496
localparam [19:0] COEFF_3 = MODE_BITS[79:60];
14971497

14981498
localparam [0:0] F_MODE = MODE_BITS[80];
1499-
localparam [2:0] OUTPUT_SELECT = 3'b100; // registered output: a * b (4)
1499+
localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4)
15001500
localparam [0:0] SATURATE_ENABLE = MODE_BITS[84];
15011501
localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85];
15021502
localparam [0:0] ROUND = MODE_BITS[91];
1503-
localparam [0:0] REGISTER_INPUTS = 1'b1; // unregistered inputs
1503+
localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs
15041504

15051505
QL_DSP3 #(
15061506
.MODE_BITS({

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