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sakumisusakumisu
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refactor(port/dwc2): support custom config for each dwc2 usb port
Signed-off-by: sakumisu <[email protected]>
1 parent 8e0ff85 commit 22e150a

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9 files changed

+1383
-516
lines changed

9 files changed

+1383
-516
lines changed

‎cherryusb_config_template.h

Lines changed: 8 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -262,28 +262,20 @@
262262

263263
// #define CONFIG_USBDEV_SOF_ENABLE
264264

265-
/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */
265+
/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode,
266+
* the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS.
267+
*
268+
* in xxx32 chips, only pb14/pb15 can support hs mode, pa11/pa12 is not supported(only a few supports, but we ignore them).
269+
*/
266270
// #define CONFIG_USB_HS
267271

268272
/* ---------------- FSDEV Configuration ---------------- */
269273
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
270274

271275
/* ---------------- DWC2 Configuration ---------------- */
272-
/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
273-
* status information) + (2 * number of OUT endpoints) + 1 for Global NAK
274-
*/
275-
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
276-
/* IN Endpoints Max packet Size / 4 */
277-
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
278-
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
279-
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
280-
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
281-
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
282-
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
283-
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
284-
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
285-
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
286-
276+
/* enable dwc2 buffer dma mode for device
277+
* in xxx32 chips, only pb14/pb15 can support dma mode, pa11/pa12 is not supported(only a few supports, but we ignore them)
278+
*/
287279
// #define CONFIG_USB_DWC2_DMA_ENABLE
288280

289281
/* ---------------- MUSB Configuration ---------------- */
@@ -320,17 +312,6 @@
320312
/* ---------------- XHCI Configuration ---------------- */
321313
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
322314

323-
/* ---------------- DWC2 Configuration ---------------- */
324-
/* largest non-periodic USB packet used / 4 */
325-
// #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4)
326-
/* largest periodic USB packet used / 4 */
327-
// #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4)
328-
/*
329-
* (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
330-
* 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
331-
*/
332-
// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
333-
334315
/* ---------------- MUSB Configuration ---------------- */
335316
// #define CONFIG_USB_MUSB_SUNXI
336317

‎core/usbd_core.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,8 @@ USB_NOCACHE_RAM_SECTION struct usbd_core_priv {
8383
uint8_t intf_altsetting[16];
8484
uint8_t intf_offset;
8585

86-
struct usbd_tx_rx_msg tx_msg[CONFIG_USBDEV_EP_NUM];
87-
struct usbd_tx_rx_msg rx_msg[CONFIG_USBDEV_EP_NUM];
86+
struct usbd_tx_rx_msg tx_msg[16];
87+
struct usbd_tx_rx_msg rx_msg[16];
8888

8989
void (*event_handler)(uint8_t busid, uint8_t event);
9090
} g_usbd_core[CONFIG_USBDEV_MAX_BUS];

‎osal/idf/usb_config.h

Lines changed: 2 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -246,92 +246,12 @@
246246
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
247247
#endif
248248

249-
/* ================ USB Device Port Configuration ================*/
250-
251249
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
252-
#define ESP_USBD_BASE 0x60080000
253-
254-
#define CONFIG_USBDEV_MAX_BUS 1
255-
// esp32s2/s3 has 7 endpoints in device mode (include ep0)
256-
#define CONFIG_USBDEV_EP_NUM 7
257-
258-
/* ---------------- DWC2 Configuration ---------------- */
259-
//esp32s2/s3 can support up to 5 IN endpoints(include ep0) at the same time
260-
#define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (320 / 4)
261-
#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
262-
#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (64 / 4)
263-
#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
264-
#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
265-
#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (64 / 4)
266-
#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (64 / 4)
267-
#define CONFIG_USB_DWC2_TX6_FIFO_SIZE (64 / 4)
268-
#define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
269-
#define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
270-
271-
#define CONFIG_USB_DWC2_DMA_ENABLE
272-
273-
#elif CONFIG_IDF_TARGET_ESP32P4
274-
#define ESP_USBD_BASE 0x50000000UL
275-
276250
#define CONFIG_USBDEV_MAX_BUS 1
277-
#define CONFIG_USBDEV_EP_NUM 7 // 16
278-
279-
/* ---------------- DWC2 Configuration ---------------- */
280-
//esp32s2/s3 can support up to 5 IN endpoints(include ep0) at the same time
281-
#define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
282-
#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
283-
#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
284-
#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (512 / 4)
285-
#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (512 / 4)
286-
#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (512 / 4)
287-
#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (64 / 4)
288-
#define CONFIG_USB_DWC2_TX6_FIFO_SIZE (64 / 4)
289-
#define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
290-
#define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
291-
292-
#define CONFIG_USB_DWC2_DMA_ENABLE
293-
#define CONFIG_USB_HS
294-
#else
295-
#error "Unsupported SoC"
296-
#endif
297-
298-
/* ================ USB Host Port Configuration ==================*/
299-
300-
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
301-
#define ESP_USBH_BASE 0x60080000
302-
303251
#define CONFIG_USBHOST_MAX_BUS 1
304-
// esp32s2/s3 has 8 endpoints in host mode (include ep0)
305-
#define CONFIG_USBHOST_PIPE_NUM 8
306-
307-
/* ---------------- DWC2 Configuration ---------------- */
308-
/* largest non-periodic USB packet used / 4 */
309-
#define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (240 / 4)
310-
/* largest periodic USB packet used / 4 */
311-
#define CONFIG_USB_DWC2_PTX_FIFO_SIZE (240 / 4)
312-
/*
313-
* (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
314-
* 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
315-
*/
316-
#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((200 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
317-
318252
#elif CONFIG_IDF_TARGET_ESP32P4
319-
#define ESP_USBH_BASE 0x50000000UL
320-
321-
#define CONFIG_USBHOST_MAX_BUS 1
322-
#define CONFIG_USBHOST_PIPE_NUM 16
323-
324-
/* ---------------- DWC2 Configuration ---------------- */
325-
/* largest non-periodic USB packet used / 4 */
326-
#define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4)
327-
/* largest periodic USB packet used / 4 */
328-
#define CONFIG_USB_DWC2_PTX_FIFO_SIZE (512 / 4)
329-
/*
330-
* (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
331-
* 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
332-
*/
333-
#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((896 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
334-
253+
#define CONFIG_USBDEV_MAX_BUS 2
254+
#define CONFIG_USBHOST_MAX_BUS 2
335255
#define CONFIG_USB_HS
336256
#else
337257
#error "Unsupported SoC"

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