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digant73digant73
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minor cleanup on interrupt functions
1 parent 9480875 commit 448f782

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6 files changed

+51
-51
lines changed

6 files changed

+51
-51
lines changed

‎TFT/src/User/Hal/buzzer.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -147,10 +147,8 @@ void Buzzer_AddSound(const uint16_t frequency, const uint16_t duration)
147147

148148
void TIMER2_IRQHandler(void) // GD32F2XX and GD32F3XX timer ISR
149149
{
150-
if ((TIMER_INTF(TIMER2) & TIMER_INTF_UPIF) != 0) // check for timer2 interrupt flag
150+
if ((TIMER_INTF(TIMER2) & TIMER_INTF_UPIF) != 0) // check for TIMER2 interrupt flag
151151
{
152-
TIMER_INTF(TIMER2) &= ~TIMER_INTF_UPIF; // clear interrupt flag
153-
154152
if (buzzer.toggles > 0) // if a sound has to be played
155153
{
156154
buzzer.toggles--;
@@ -168,6 +166,8 @@ void TIMER2_IRQHandler(void) // GD32F2XX and GD32F3XX timer ISR
168166
buzzer.toggles++; // silence, no toggling, only counting
169167
}
170168
}
169+
170+
TIMER_INTF(TIMER2) &= ~TIMER_INTF_UPIF; // as last, clear TIMER2 interrupt flag
171171
}
172172
}
173173

@@ -177,8 +177,6 @@ void TIM3_IRQHandler(void) // STM32FXX timer ISR
177177
{
178178
if ((TIM3->SR & TIM_SR_UIF) != 0) // check for TIM3 interrupt flag
179179
{
180-
TIM3->SR &= ~TIM_SR_UIF; // clear interrupt flag
181-
182180
if (buzzer.toggles > 0) // if a sound has to be played
183181
{
184182
buzzer.toggles--;
@@ -196,6 +194,8 @@ void TIM3_IRQHandler(void) // STM32FXX timer ISR
196194
buzzer.toggles++; // silence, no toggling, only counting
197195
}
198196
}
197+
198+
TIM3->SR &= ~TIM_SR_UIF; // as last, clear TIM3 interrupt flag
199199
}
200200
}
201201

‎TFT/src/User/Hal/gd32f20x/Serial.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -274,40 +274,40 @@ void Serial_Put(uint8_t port, const char * msg)
274274
void USART_IRQHandler(uint8_t port)
275275
{
276276
#if IDLE_LINE_IT == true // IDLE Line interrupt
277-
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET) // check for IDLE Line interrupt
277+
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET) // check for IDLE Line interrupt flag
278278
{
279-
USART_STAT0(Serial[port].uart); // clear IDLE Line bit
280-
USART_DATA(Serial[port].uart);
281-
282279
dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelRX);
280+
281+
USART_DATA(Serial[port].uart); // clear RXNE pending flag
282+
USART_STAT0(Serial[port].uart); // as last, clear IDLE Line interrupt flag
283283
}
284284
#endif
285285

286286
#ifdef TX_DMA_WRITE // TX DMA based serial writing
287-
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET) // check for Transfer Complete (TC) interrupt
287+
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET) // check for Transfer Complete (TC) interrupt flag
288288
{
289-
USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC; // clear Transfer Complete (TC) bit
290-
291289
// NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
292290
// NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
293291
//
294292
if (DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelTX) == 0) // sending is complete
295293
{
296294
// NOTE: it marks message timestamp twice if transfer was split into 2 parts
297-
dmaL1DataTX[port].timestamp = OS_GetTimeMs(); // keep track of last sent message timestamp
295+
dmaL1DataTX[port].timestamp = OS_GetTimeMs(); // keep track of last sent message timestamp
298296

299297
dmaL1DataTX[port].rIndex = (dmaL1DataTX[port].rIndex + dmaL1DataTX[port].flag) % dmaL1DataTX[port].cacheSize;
300298
dmaL1DataTX[port].flag = 0;
301299

302-
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
303-
Serial_Send_TX(port); // continue sending data
300+
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
301+
Serial_Send_TX(port); // continue sending data
304302
else
305-
USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do
303+
USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do
306304
}
307305
// else: more data is coming, wait for next Transfer Complete (TC) interrupt
306+
307+
USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC; // as last, clear Transfer Complete (TC) interrupt flag
308308
}
309309
#else // TX interrupt based serial writing
310-
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET) // check for TBE interrupt
310+
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET) // check for TBE interrupt flag
311311
{
312312
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
313313
{

‎TFT/src/User/Hal/gd32f30x/Serial.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -264,40 +264,40 @@ void Serial_Put(uint8_t port, const char * msg)
264264
void USART_IRQHandler(uint8_t port)
265265
{
266266
#if IDLE_LINE_IT == true // IDLE Line interrupt
267-
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET) // check for IDLE Line interrupt
267+
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET) // check for IDLE Line interrupt flag
268268
{
269-
USART_STAT0(Serial[port].uart); // clear IDLE Line bit
270-
USART_DATA(Serial[port].uart);
271-
272269
dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelRX);
270+
271+
USART_DATA(Serial[port].uart); // clear RXNE pending flag
272+
USART_STAT0(Serial[port].uart); // as last, clear IDLE Line interrupt flag
273273
}
274274
#endif
275275

276276
#ifdef TX_DMA_WRITE // TX DMA based serial writing
277-
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET) // check for Transfer Complete (TC) interrupt
277+
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET) // check for Transfer Complete (TC) interrupt flag
278278
{
279-
USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC; // clear Transfer Complete (TC) bit
280-
281279
// NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
282280
// NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
283281
//
284282
if (DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelTX) == 0) // sending is complete
285283
{
286284
// NOTE: it marks message timestamp twice if transfer was split into 2 parts
287-
dmaL1DataTX[port].timestamp = OS_GetTimeMs(); // keep track of last sent message timestamp
285+
dmaL1DataTX[port].timestamp = OS_GetTimeMs(); // keep track of last sent message timestamp
288286

289287
dmaL1DataTX[port].rIndex = (dmaL1DataTX[port].rIndex + dmaL1DataTX[port].flag) % dmaL1DataTX[port].cacheSize;
290288
dmaL1DataTX[port].flag = 0;
291289

292-
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
293-
Serial_Send_TX(port); // continue sending data
290+
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
291+
Serial_Send_TX(port); // continue sending data
294292
else
295-
USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do
293+
USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do
296294
}
297295
// else: more data is coming, wait for next Transfer Complete (TC) interrupt
296+
297+
USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC; // as last, clear Transfer Complete (TC) interrupt flag
298298
}
299299
#else // TX interrupt based serial writing
300-
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET) // check for TBE interrupt
300+
if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET) // check for TBE interrupt flag
301301
{
302302
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
303303
{

‎TFT/src/User/Hal/stm32f10x/Serial.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -241,20 +241,18 @@ void Serial_Put(uint8_t port, const char * msg)
241241
void USART_IRQHandler(uint8_t port)
242242
{
243243
#if IDLE_LINE_IT == true // IDLE Line interrupt
244-
if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt
244+
if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt flag
245245
{
246-
Serial[port].uart->SR; // clear IDLE Line bit
247-
Serial[port].uart->DR;
246+
dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_streamRX->NDTR;
248247

249-
dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_channelRX->CNDTR;
248+
Serial[port].uart->DR; // clear RXNE pending flag
249+
Serial[port].uart->SR; // as last, clear IDLE Line interrupt flag
250250
}
251251
#endif
252252

253253
#ifdef TX_DMA_WRITE // TX DMA based serial writing
254-
if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt
254+
if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt flag
255255
{
256-
Serial[port].uart->SR &= ~USART_SR_TC; // clear Transfer Complete (TC) bit
257-
258256
// NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
259257
// NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
260258
//
@@ -272,9 +270,11 @@ void USART_IRQHandler(uint8_t port)
272270
Serial[port].uart->CR1 &= ~USART_CR1_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do
273271
}
274272
// else: more data is coming, wait for next Transfer Complete (TC) interrupt
273+
274+
Serial[port].uart->SR &= ~USART_SR_TC; // as last, clear Transfer Complete (TC) interrupt flag
275275
}
276276
#else // TX interrupt based serial writing
277-
if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt
277+
if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt flag
278278
{
279279
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
280280
{

‎TFT/src/User/Hal/stm32f2_f4xx/Serial.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -292,20 +292,18 @@ void Serial_Put(uint8_t port, const char * msg)
292292
void USART_IRQHandler(uint8_t port)
293293
{
294294
#if IDLE_LINE_IT == true // IDLE Line interrupt
295-
if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt
295+
if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt flag
296296
{
297-
Serial[port].uart->SR; // clear IDLE Line bit
298-
Serial[port].uart->DR;
299-
300297
dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_streamRX->NDTR;
298+
299+
Serial[port].uart->DR; // clear RXNE pending flag
300+
Serial[port].uart->SR; // as last, clear IDLE Line interrupt flag
301301
}
302302
#endif
303303

304304
#ifdef TX_DMA_WRITE // TX DMA based serial writing
305-
if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt
305+
if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt flag
306306
{
307-
Serial[port].uart->SR &= ~USART_SR_TC; // clear Transfer Complete (TC) bit
308-
309307
// NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
310308
// NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
311309
//
@@ -323,9 +321,11 @@ void USART_IRQHandler(uint8_t port)
323321
Serial[port].uart->CR1 &= ~USART_CR1_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do
324322
}
325323
// else: more data is coming, wait for next Transfer Complete (TC) interrupt
324+
325+
Serial[port].uart->SR &= ~USART_SR_TC; // as last, clear Transfer Complete (TC) interrupt flag
326326
}
327327
#else // TX interrupt based serial writing
328-
if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt
328+
if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt flag
329329
{
330330
if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?
331331
{

‎TFT/src/User/os_timer.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,8 @@ void OS_InitTimerMs(void)
3636

3737
void TIMER6_IRQHandler(void)
3838
{
39-
if ((TIMER_INTF(TIMER6) & TIMER_INTF_UPIF) != 0)
39+
if ((TIMER_INTF(TIMER6) & TIMER_INTF_UPIF) != 0) // check for TIMER6 interrupt flag
4040
{
41-
TIMER_INTF(TIMER6) &= ~TIMER_INTF_UPIF; // clear interrupt flag
42-
4341
os_counter.ms++;
4442
os_counter.sec--;
4543

@@ -53,17 +51,17 @@ void TIMER6_IRQHandler(void)
5351
}
5452

5553
TS_CheckPress(); // check touch screen once a millisecond
54+
55+
TIMER_INTF(TIMER6) &= ~TIMER_INTF_UPIF; // as last, clear TIMER6 interrupt flag
5656
}
5757
}
5858

5959
#else
6060

6161
void TIM7_IRQHandler(void)
6262
{
63-
if ((TIM7->SR & TIM_SR_UIF) != 0)
63+
if ((TIM7->SR & TIM_SR_UIF) != 0) // check for TIM7 interrupt flag
6464
{
65-
TIM7->SR &= ~TIM_SR_UIF; // clear interrupt flag
66-
6765
os_counter.ms++;
6866
os_counter.sec--;
6967

@@ -77,6 +75,8 @@ void TIM7_IRQHandler(void)
7775
}
7876

7977
TS_CheckPress(); // check touch screen once a millisecond
78+
79+
TIM7->SR &= ~TIM_SR_UIF; // as last, clear TIM7 interrupt flag
8080
}
8181
}
8282

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