Fix/component catalog (#870)

* Fixed components_catalog load

* Fixed components_catalog load

* Fixed example

* Fixed example

* removed unused definitions

* improved props

* Improved Coverage of UT

* Black Fix

* Black Fix

Co-authored-by: maxcapodi78 <Shark78>

Author: maxcapodi78

_unittest/test_21_Circuit.py

@@ -310,3 +310,4 @@ def test_26_component_catalog(self):
         assert isinstance(comp_catalog.find_components("cap"), list)
         assert comp_catalog["LISN:CISPR25_LISN"].place("Lisn1")
         assert not comp_catalog["Capacitors"]
+        assert comp_catalog["LISN:CISPR25_LISN"].props

_unittest/test_34_TwinBuilder.py

@@ -66,3 +66,9 @@ def test_10_set_hmin(self):
 
     def test_11_set_end_time(self):
         assert self.aedtapp.set_end_time("5s")
+
+    def test_12_catalog(self):
+        comp_catalog = self.aedtapp.modeler.components.components_catalog
+        assert not comp_catalog["Capacitors"]
+        assert comp_catalog["Aircraft Electrical VHDLAMS\\Basic:lowpass_filter"].props
+        assert comp_catalog["Aircraft Electrical VHDLAMS\\Basic:lowpass_filter"].place("LP1")

examples/06-Multiphysics/Hfss_Icepak_Coupling.py

@@ -314,10 +314,7 @@
 # ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # This example use Matplotlib and Numpy to generate graphs outside of PyAEDT.
 
-trace_names = []
-for el in portnames:
-    for el2 in portnames:
-        trace_names.append("S(" + el + "," + el2 + ")")
+trace_names = aedtapp.get_traces_for_plot(category="S")
 cxt = ["Domain:=", "Sweep"]
 families = ["Freq:=", ["All"]]
 my_data = aedtapp.post.get_report_data(expression=trace_names)

pyaedt/edb.py

@@ -1084,6 +1084,7 @@ def create_cutout_on_point_list(
         #                 if pad.parameters_values:
         #                     point2 = self.edb.Geometry.PointData(self.edb_value(posx + 3 * pad.parameters_values[0]),
         #                                                          self.edb_value(posy + 3 * pad.parameters_values[0]))
+        #
         #                     point3 = self.edb.Geometry.PointData(self.edb_value(posx - 3 * pad.parameters_values[0]),
         #                                                          self.edb_value(posy - 3 * pad.parameters_values[0]))
         #                     if polygonData.PointInPolygon(
@@ -1094,12 +1095,11 @@ def create_cutout_on_point_list(
         #                     if polygonData.GetIntersectionType(pad.polygon_data) >= 1:
         #                         via_lists.append(via)
         #                         break
-
         _netsClip = convert_py_list_to_net_list(_ref_nets)
         net_signals = List[type(_ref_nets[0])]()
         # Create new cutout cell/design
         _cutout = self.active_cell.CutOut(net_signals, _netsClip, polygonData)
-
+        self._active_cell
         # TODO check and insert via check on polygon intersection
         # if add_vias_on_cutout:
         #     layout = _cutout.GetLayout()

pyaedt/generic/LoadAEDTFile.py

@@ -34,7 +34,7 @@ def load_keyword_in_aedt_file(filename, keyword):
 
     Returns
     -------
-    type
+    dict
         dictionary containing the decoded AEDT file
 
     """

pyaedt/generic/general_methods.py

@@ -575,7 +575,7 @@ def filter_string(value, search_key1):
     ignore_case = True
 
     def _create_pattern(k1):
-        k1a = re.sub(r"\?", r".", k1)
+        k1a = re.sub(r"\?", r".", k1.replace("\\", "\\\\"))
         k1b = re.sub(r"\*", r".*?", k1a)
         pattern = r"^{}$".format(k1b)
         return pattern

pyaedt/modeler/PrimitivesCircuit.py

@@ -14,7 +14,7 @@
 from pyaedt.modeler.Object3d import CircuitComponent
 from pyaedt.generic.constants import AEDT_UNITS
 from pyaedt.generic.TouchstoneParser import _parse_ports_name
-from pyaedt.generic.LoadAEDTFile import load_entire_aedt_file
+from pyaedt.generic.LoadAEDTFile import load_keyword_in_aedt_file
 
 
 class CircuitComponents(object):
@@ -1242,12 +1242,21 @@ def arg_with_dim(self, Value, sUnits=None):
 class ComponentInfo(object):
     """Class that manage Circuit Catalog info."""
 
-    def __init__(self, name, component_manager, props):
+    def __init__(self, name, component_manager, file_name, component_library):
         self._component_manager = component_manager
-        self.props = props
+        self.file_name = file_name
         self.name = name
-        self.component_library = self.props.get("ComponentLibrary", None)
+        self.component_library = component_library
+        self._props = None
 
+    @property
+    def props(self):
+        """Retrieve the component properties."""
+        if not self._props:
+            self._props = load_keyword_in_aedt_file(self.file_name, self.name)
+        return self._props
+
+    @aedt_exception_handler
     def place(self, inst_name, location=[], angle=0, use_instance_id_netlist=False):
         """Create a component from a library.
 
@@ -1326,19 +1335,20 @@ def _index_components(self, library_path=None):
             sys_files = recursive_glob(os.path.join(self._app.syslib, self._component_manager.design_libray), "*.aclb")
             root = os.path.normpath(self._app.syslib).split(os.path.sep)[-1]
         for file in sys_files:
-            comps = load_entire_aedt_file(file)
+            comps1 = load_keyword_in_aedt_file(file, "DefInfo")
+            comps2 = load_keyword_in_aedt_file(file, "CompInfo")
+            comps = comps1.get("DefInfo", {})
+            comps.update(comps2.get("CompInfo", {}))
             for compname, comp_value in comps.items():
-                if compname not in ["$base_index$", "$index$", "DefInfo"]:
-                    root_name, ext = os.path.splitext(os.path.basename(file))
-                    full_path = os.path.normpath(file).split(os.path.sep)
-                    id = full_path.index(root) + 1
-                    if self._component_manager.design_libray in full_path[id:]:
-                        id += 1
-                    full_path[-1] = full_path[-1].replace(".aclb", "")
-                    comp_value["ComponentLibrary"] = "\\".join(full_path[id:])
-                    self.components["{}:{}".format(root_name, compname)] = ComponentInfo(
-                        compname, self._component_manager, comp_value
-                    )
+                root_name, ext = os.path.splitext(os.path.normpath(file))
+                full_path = root_name.split(os.path.sep)
+                id = full_path.index(root) + 1
+                if self._component_manager.design_libray in full_path[id:]:
+                    id += 1
+                comp_lib = "\\".join(full_path[id:]) + ":" + compname
+                self.components[comp_lib] = ComponentInfo(
+                    compname, self._component_manager, file, comp_lib.split(":")[0]
+                )
 
     @aedt_exception_handler
     def find_components(self, filter_str="*"):

pyaedt/modeler/PrimitivesSimplorer.py

@@ -22,6 +22,10 @@ class SimplorerComponents(CircuitComponents):
     >>> prim = aedtapp.modeler.schematic
     """
 
+    @property
+    def _logger(self):
+        return self._app.logger
+
     @property
     def design_libray(self):
         """Design Library."""