Skip to content

Commit 84f3516

Browse files
committed
Merge branch 'main' into create_rectangle
2 parents 01dc20a + 744c92c commit 84f3516

File tree

20 files changed

+2538
-403
lines changed

20 files changed

+2538
-403
lines changed

_unittest/test_00_EDB.py

Lines changed: 29 additions & 163 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44

55
from pyaedt import Edb
66
from pyaedt.edb_core.components import resistor_value_parser
7-
from pyaedt.generic.constants import SourceType
7+
from pyaedt.edb_core.EDB_Data import SimulationConfiguration
88

99
# Setup paths for module imports
1010
# Import required modules
@@ -32,7 +32,9 @@ def setup_class(self):
3232
self.local_scratch.copyfolder(example_project2, self.target_path2)
3333

3434
def teardown_class(self):
35-
BasisTest.my_teardown(self)
35+
self.edbapp.close_edb()
36+
self.local_scratch.remove()
37+
del self.edbapp
3638

3739
def test_00_export_ipc2581(self):
3840
ipc_path = os.path.join(self.local_scratch.path, "test.xml")
@@ -65,35 +67,12 @@ def test_01_find_by_name(self):
6567
assert isinstance(parameters[1], list)
6668
assert isinstance(parameters[0], int)
6769

68-
def test_01A_create_ports(self):
69-
pins = self.edbapp.core_components.get_pin_from_component("J1")
70-
nets = self.edbapp.core_components.get_nets_from_pin_list(pins)
71-
assert len(nets) == 6
72-
assert "IO13_ICSP_R" in nets
73-
assert "V5_ALW_ON" in nets
74-
assert "GND" in nets
75-
assert "IO11_ICSP_R" in nets
76-
assert "RESET_N_SHLD" in nets
77-
assert "IO12_ICSP_R" in nets
78-
79-
assert self.edbapp.core_components.create_port_on_component(
80-
component="J1", net_list=nets[:2], port_type=SourceType.CoaxPort, do_pingroup=True, reference_net="GND"
81-
)
82-
assert self.edbapp.core_components.create_port_on_component(
83-
component="J1", net_list=nets[3], port_type=SourceType.CoaxPort, do_pingroup=False, reference_net="GND"
84-
)
85-
assert self.edbapp.core_components.create_port_on_component(
86-
component="J1", net_list=nets[-2:], port_type=SourceType.CircPort, do_pingroup=False, reference_net="GND"
87-
)
88-
8970
def test_01B_get_vias_from_nets(self):
9071
assert self.edbapp.core_padstack.get_via_instance_from_net("GND")
9172
assert not self.edbapp.core_padstack.get_via_instance_from_net(["GND2"])
9273

93-
def test_01C_create_lumped_port_at_location(self):
94-
assert self.edbapp.core_hfss.create_lumped_port_on_trace(
95-
nets="M_DQ<11>", reference_layer="GND", point_list=[(17.169892e-3, 38.874954e-3)]
96-
)
74+
def test_01C_create_coax_port_on_component(self):
75+
assert self.edbapp.core_hfss.create_coax_port_on_component("U1A1", "M_DQS_N<1>")
9776

9877
def test_02_get_properties(self):
9978
assert len(self.edbapp.core_components.components) > 0
@@ -625,9 +604,8 @@ def test_67_add_void(self):
625604

626605
def test_69_create_solder_balls_on_component(self):
627606
assert self.edbapp.core_components.set_solder_ball("U2A5")
628-
assert self.edbapp.core_components.set_solder_ball("U2A5", "100um", "150um")
629607

630-
@pytest.mark.skipif(is_ironpython, reason="This Test uses Matplotlib that is not supported by Ironpython")
608+
@pytest.mark.skipif(is_ironpython, reason="This test uses Matplotlib, which is not supported by IronPython.")
631609
def test_70_plot_on_matplotlib(self):
632610
local_png = os.path.join(self.local_scratch.path, "test.png")
633611
self.edbapp.core_nets.plot(None, None, save_plot=local_png)
@@ -760,124 +738,6 @@ def test_79_get_placement_vector(self):
760738
edb2.close_edb()
761739
del edb2
762740

763-
def test_79b_get_placement_vector(self):
764-
laminate_edb = Edb(
765-
os.path.join(local_path, "example_models", "lam_for_bottom_place.aedb"), edbversion=desktop_version
766-
)
767-
chip_edb = Edb(os.path.join(local_path, "example_models", "chip.aedb"), edbversion=desktop_version)
768-
try:
769-
laminate_cmp = laminate_edb.core_components.get_component_by_name("U3")
770-
chip_cmp = chip_edb.core_components.get_component_by_name("U1")
771-
result, vector, rotation, solder_ball_height = laminate_edb.core_components.get_component_placement_vector(
772-
chip_cmp, laminate_cmp, "1", "2", "1", "2", True
773-
)
774-
assert result
775-
assert abs(rotation - math.pi / 2) < 1e-9
776-
assert solder_ball_height == 0
777-
assert abs(vector[0] - 0.5e-3) < 1e-9
778-
assert abs(vector[1] + 0.5e-3) < 1e-9
779-
finally:
780-
chip_edb.close_edb()
781-
laminate_edb.close_edb()
782-
783-
def test_79c_get_placement_vector(self):
784-
laminate_edb = Edb(
785-
os.path.join(local_path, "example_models", "lam_for_bottom_place.aedb"), edbversion=desktop_version
786-
)
787-
chip_edb = Edb(os.path.join(local_path, "example_models", "chip.aedb"), edbversion=desktop_version)
788-
try:
789-
laminate_cmp = laminate_edb.core_components.get_component_by_name("U1")
790-
chip_cmp = chip_edb.core_components.get_component_by_name("U1")
791-
result, vector, rotation, solder_ball_height = laminate_edb.core_components.get_component_placement_vector(
792-
chip_cmp, laminate_cmp, "1", "2", "1", "2"
793-
)
794-
assert result
795-
assert abs(rotation) < 1e-9
796-
assert solder_ball_height == 0
797-
assert abs(vector[0]) < 1e-9
798-
assert abs(vector[1]) < 1e-9
799-
finally:
800-
chip_edb.close_edb()
801-
laminate_edb.close_edb()
802-
803-
def test_79d_get_placement_vector_offset(self):
804-
laminate_edb = Edb(
805-
os.path.join(local_path, "example_models", "lam_for_bottom_place.aedb"), edbversion=desktop_version
806-
)
807-
chip_edb = Edb(os.path.join(local_path, "example_models", "chip_offset.aedb"), edbversion=desktop_version)
808-
try:
809-
laminate_cmp = laminate_edb.core_components.get_component_by_name("U3")
810-
chip_cmp = chip_edb.core_components.get_component_by_name("U1")
811-
result, vector, rotation, solder_ball_height = laminate_edb.core_components.get_component_placement_vector(
812-
chip_cmp, laminate_cmp, "1", "4", "1", "4", True
813-
)
814-
assert result
815-
assert abs(rotation - math.pi / 2) < 1e-9
816-
assert solder_ball_height == 0
817-
assert abs(vector[0] - 0.2e-3) < 1e-9
818-
assert abs(vector[1] + 0.8e-3) < 1e-9
819-
finally:
820-
chip_edb.close_edb()
821-
laminate_edb.close_edb()
822-
823-
def test_79e_get_placement_vector_offset(self):
824-
laminate_edb = Edb(
825-
os.path.join(local_path, "example_models", "lam_for_bottom_place.aedb"), edbversion=desktop_version
826-
)
827-
chip_edb = Edb(os.path.join(local_path, "example_models", "chip_offset.aedb"), edbversion=desktop_version)
828-
try:
829-
laminate_cmp = laminate_edb.core_components.get_component_by_name("U1")
830-
chip_cmp = chip_edb.core_components.get_component_by_name("U1")
831-
result, vector, rotation, solder_ball_height = laminate_edb.core_components.get_component_placement_vector(
832-
chip_cmp, laminate_cmp, "1", "4", "1", "4"
833-
)
834-
assert result
835-
assert abs(rotation) < 1e-9
836-
assert solder_ball_height == 0
837-
assert abs(vector[0] - 0.3e-3) < 1e-9
838-
assert abs(vector[1] - 0.3e-3) < 1e-9
839-
finally:
840-
chip_edb.close_edb()
841-
laminate_edb.close_edb()
842-
843-
def test_79f_get_placement_vector_offset(self):
844-
laminate_edb = Edb(
845-
os.path.join(local_path, "example_models", "lam_for_top_place.aedb"), edbversion=desktop_version
846-
)
847-
chip_edb = Edb(os.path.join(local_path, "example_models", "chip_offset.aedb"), edbversion=desktop_version)
848-
try:
849-
laminate_cmp = laminate_edb.core_components.get_component_by_name("U3")
850-
chip_cmp = chip_edb.core_components.get_component_by_name("U1")
851-
result, vector, rotation, solder_ball_height = laminate_edb.core_components.get_component_placement_vector(
852-
chip_cmp, laminate_cmp, "1", "4", "1", "4", False
853-
)
854-
assert result
855-
assert abs(rotation - math.pi / 2) < 1e-9
856-
assert solder_ball_height == 0
857-
assert abs(vector[0] - 0.8e-3) < 1e-9
858-
assert abs(vector[1] + 0.8e-3) < 1e-9
859-
finally:
860-
chip_edb.close_edb()
861-
laminate_edb.close_edb()
862-
863-
def test_79g_get_placement_vector(self):
864-
board_edb = Edb(os.path.join(local_path, "example_models", "invert_board.aedb"), edbversion=desktop_version)
865-
package_edb = Edb(os.path.join(local_path, "example_models", "package2.aedb"), edbversion=desktop_version)
866-
try:
867-
laminate_cmp = board_edb.core_components.get_component_by_name("U100")
868-
chip_cmp = package_edb.core_components.get_component_by_name("BGA")
869-
result, vector, rotation, solder_ball_height = board_edb.core_components.get_component_placement_vector(
870-
chip_cmp, laminate_cmp, "A12", "A14", "A12", "A14", True
871-
)
872-
assert result
873-
assert abs(rotation) < 1e-9
874-
assert abs(solder_ball_height - 315e-6) < 1e-9
875-
assert abs(vector[0] + 48.7e-3) < 10e-9
876-
assert abs(vector[1] - 59.7e-3) < 10e-9
877-
finally:
878-
package_edb.close_edb()
879-
board_edb.close_edb()
880-
881741
def test_80_edb_without_path(self):
882742
edbapp_without_path = Edb(edbversion=desktop_version, isreadonly=False)
883743
time.sleep(2)
@@ -894,22 +754,12 @@ def test_80_create_rectangle_in_pad(self):
894754
edb_padstacks = Edb(
895755
edbpath=os.path.join(self.local_scratch.path, "padstacks2.aedb"),
896756
edbversion=desktop_version,
897-
isreadonly=False,
757+
isreadonly=True,
898758
)
899759
for i in range(7):
900760
padstack_instance = list(edb_padstacks.core_padstack.padstack_instances.values())[i]
901761
result = padstack_instance.create_rectangle_in_pad("s")
902762
assert result
903-
points = padstack_instance.create_rectangle_in_pad("s", return_points=True)
904-
assert len(points) == 4
905-
assert len(points[0]) == 2
906-
# for i in range(8, 10):
907-
# padstack_instance = list(edb_padstacks.core_padstack.padstack_instances.values())[i]
908-
# result = padstack_instance.create_rectangle_in_pad("g")
909-
# assert result
910-
# points = padstack_instance.create_rectangle_in_pad("g", return_points=True)
911-
# assert len(points) == 4
912-
# assert len(points[0]) == 2
913763
edb_padstacks.close_edb()
914764

915765
def test_81_edb_with_dxf(self):
@@ -1077,7 +927,27 @@ def test_82c_place_on_bottom_of_lam_with_mold_solder(self):
1077927
chipEdb.close_edb()
1078928
laminateEdb.close_edb()
1079929

1080-
def test_83_set_component_type(self):
930+
def test_83_build_siwave_project_from_config_file(self):
931+
cfg_file = os.path.join(os.path.dirname(self.edbapp.edbpath), "test.cfg")
932+
with open(cfg_file, "w") as f:
933+
f.writelines("SolverType = 'Siwave'\n")
934+
f.writelines("PowerNets = ['GND']\n")
935+
f.writelines("Components = ['U2A5', 'U1B5']")
936+
937+
sim_config = SimulationConfiguration(cfg_file)
938+
assert self.edbapp.build_simulation_project(sim_config)
939+
940+
def test_84_build_hfss_project_from_config_file(self):
941+
cfg_file = os.path.join(os.path.dirname(self.edbapp.edbpath), "test.cfg")
942+
with open(cfg_file, "w") as f:
943+
f.writelines("SolverType = 'Hfss3dLayout'\n")
944+
f.writelines("PowerNets = ['GND']\n")
945+
f.writelines("Components = ['U2A5', 'U1B5']")
946+
947+
sim_config = SimulationConfiguration(cfg_file)
948+
assert self.edbapp.build_simulation_project(sim_config)
949+
950+
def test_85_set_component_type(self):
1081951
comp = self.edbapp.core_components.components["R2L18"]
1082952
comp.type = "Resistor"
1083953
assert comp.type == "Resistor"
@@ -1092,10 +962,6 @@ def test_83_set_component_type(self):
1092962
comp.type = "Other"
1093963
assert comp.type == "Other"
1094964

1095-
def test_84_create_coax_port_on_component_pin(self):
1096-
assert self.edbapp.core_hfss.create_coax_port_on_component_per_pin("U1A1", "D1", "port1")
1097-
assert self.edbapp.core_hfss.create_coax_port_on_component_per_net("U1A1", "M_DQS_N<1>", "port2")
1098-
1099965
def test_85_deactivate_rlc(self):
1100966
assert self.edbapp.core_components.deactivate_rlc_component(component="C1", create_circuit_port=True)
1101967
assert self.edbapp.core_components.deactivate_rlc_component(component="C2", create_circuit_port=False)

_unittest/test_32_RMxprt.py

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,31 @@ def test_02_changeesolution(self):
2828
assert self.aedtapp.disable_modelcreation("LSSM")
2929
assert self.aedtapp.enable_modelcreation("WRIM")
3030

31-
def test_06a_create_setup(self):
31+
def test_03_getchangeproperty(self):
32+
# test increment statorOD by 1mm
33+
self.aedtapp.disable_modelcreation("ASSM")
34+
statorOD = self.aedtapp.stator["Outer Diameter"]
35+
assert statorOD
36+
self.aedtapp.stator["Outer Diameter"] = statorOD + "+1mm"
37+
38+
def test_04_create_setup(self):
39+
# first test GRM (use Inner-Rotor Induction Machine)
40+
assert self.aedtapp.enable_modelcreation("IRIM")
3241
mysetup = self.aedtapp.create_setup()
42+
assert mysetup.props["RatedOutputPower"]
3343
mysetup.props["RatedOutputPower"] = "100W"
34-
assert mysetup.update()
44+
assert mysetup.update() # update only needed for assertion
45+
# second test ASSM setup
46+
self.aedtapp.delete_setup(mysetup.name)
47+
assert self.aedtapp.disable_modelcreation("ASSM")
48+
mysetup = self.aedtapp.create_setup()
49+
assert mysetup.props["RatedSpeed"]
50+
mysetup.props["RatedSpeed"] = "3600rpm"
51+
assert mysetup.update() # update only needed for assertion
52+
# third test TPSM/SYNM setup
53+
self.aedtapp.delete_setup(mysetup.name)
54+
assert self.aedtapp.disable_modelcreation("TPSM")
55+
mysetup = self.aedtapp.create_setup()
56+
assert mysetup.props["RatedVoltage"]
57+
mysetup.props["RatedVoltage"] = "208V"
58+
assert mysetup.update() # update only needed for assertion

pyaedt/application/design_solutions.py

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,7 @@
345345
"ORIM": {"name": "ORIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
346346
"SRIM": {"name": "SRIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
347347
"WRIM": {"name": "WRIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
348-
"DFIG": {"name": "DFIG", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
348+
"DFIG": {"name": "DFIG", "options": None, "report_type": None, "default_setup": 43, "default_adaptive": None},
349349
"AFIM": {"name": "AFIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
350350
"HM": {"name": "HM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
351351
"RFSM": {"name": "RFSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
@@ -355,18 +355,18 @@
355355
"APSM": {"name": "APSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
356356
"IBDM": {"name": "IBDM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
357357
"ABDM": {"name": "ABDM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
358-
"TPIM": {"name": "TPIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
359-
"SPIM": {"name": "SPIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
360-
"TPSM": {"name": "TPSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
361-
"BLDC": {"name": "BLDC", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
362-
"ASSM": {"name": "ASSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
363-
"PMDC": {"name": "PMDC", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
364-
"SRM": {"name": "SRM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
365-
"LSSM": {"name": "LSSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
366-
"UNIM": {"name": "UNIM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
367-
"DCM": {"name": "DCM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
368-
"CPSM": {"name": "CPSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
369-
"NSSM": {"name": "NSSM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},
358+
"TPIM": {"name": "TPIM", "options": None, "report_type": None, "default_setup": 44, "default_adaptive": None},
359+
"SPIM": {"name": "SPIM", "options": None, "report_type": None, "default_setup": 45, "default_adaptive": None},
360+
"TPSM": {"name": "SYNM", "options": None, "report_type": None, "default_setup": 46, "default_adaptive": None},
361+
"BLDC": {"name": "BLDC", "options": None, "report_type": None, "default_setup": 47, "default_adaptive": None},
362+
"ASSM": {"name": "ASSM", "options": None, "report_type": None, "default_setup": 48, "default_adaptive": None},
363+
"PMDC": {"name": "PMDC", "options": None, "report_type": None, "default_setup": 49, "default_adaptive": None},
364+
"SRM": {"name": "SRM", "options": None, "report_type": None, "default_setup": 50, "default_adaptive": None},
365+
"LSSM": {"name": "LSSM", "options": None, "report_type": None, "default_setup": 51, "default_adaptive": None},
366+
"UNIM": {"name": "UNIM", "options": None, "report_type": None, "default_setup": 52, "default_adaptive": None},
367+
"DCM": {"name": "DCM", "options": None, "report_type": None, "default_setup": 53, "default_adaptive": None},
368+
"CPSM": {"name": "CPSM", "options": None, "report_type": None, "default_setup": 54, "default_adaptive": None},
369+
"NSSM": {"name": "NSSM", "options": None, "report_type": None, "default_setup": 55, "default_adaptive": None},
370370
},
371371
"ModelCreation": {
372372
"GRM": {"name": "GRM", "options": None, "report_type": None, "default_setup": 34, "default_adaptive": None},

0 commit comments

Comments
 (0)