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FIX: Fix equivalent circuit export (#6139)
Co-authored-by: pyansys-ci-bot <[email protected]>
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3 files changed

+48
-31
lines changed

3 files changed

+48
-31
lines changed

doc/changelog.d/6139.fixed.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Fix equivalent circuit export

src/ansys/aedt/core/q3d.py

Lines changed: 35 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1121,45 +1121,49 @@ def export_equivalent_circuit(
11211121
else:
11221122
circuit_settings = self.oanalysis.GetCircuitSettings()
11231123
for setting in circuit_settings:
1124-
if isinstance(setting, tuple):
1124+
if isinstance(setting, tuple) or isinstance(setting, list):
11251125
if setting[0] == "NAME:CPPInfo":
11261126
cpp_settings = setting
1127-
1127+
break
11281128
if self.modeler._is3d:
11291129
try:
1130+
export_circuit_context = [
1131+
"NAME:CircuitData",
1132+
"MatrixName:=",
1133+
matrix,
1134+
"NumberOfCells:=",
1135+
str(cells),
1136+
"UserHasChangedSettings:=",
1137+
user_changed_settings,
1138+
"IncludeCap:=",
1139+
include_cap,
1140+
"IncludeCond:=",
1141+
include_cond,
1142+
coupling_limits,
1143+
"IncludeDCR:=",
1144+
include_dcr,
1145+
"IncudeDCL:=",
1146+
include_dcl,
1147+
"IncludeACR:=",
1148+
include_acr,
1149+
"IncludeACL:=",
1150+
include_acl,
1151+
"ADDResistance:=",
1152+
add_resistance,
1153+
"ParsePinNames:=",
1154+
parse_pin_names,
1155+
]
1156+
1157+
if include_cpp:
1158+
export_circuit_context.append("IncludeCPP:=")
1159+
export_circuit_context.append(include_cpp)
1160+
export_circuit_context.append(cpp_settings)
1161+
11301162
self.oanalysis.ExportCircuit(
11311163
analysis_setup,
11321164
variations,
11331165
output_file,
1134-
[
1135-
"NAME:CircuitData",
1136-
"MatrixName:=",
1137-
matrix,
1138-
"NumberOfCells:=",
1139-
str(cells),
1140-
"UserHasChangedSettings:=",
1141-
user_changed_settings,
1142-
"IncludeCap:=",
1143-
include_cap,
1144-
"IncludeCond:=",
1145-
include_cond,
1146-
[coupling_limits],
1147-
"IncludeDCR:=",
1148-
include_dcr,
1149-
"IncudeDCL:=",
1150-
include_dcl,
1151-
"IncludeACR:=",
1152-
include_acr,
1153-
"IncludeACL:=",
1154-
include_acl,
1155-
"ADDResistance:=",
1156-
add_resistance,
1157-
"ParsePinNames:=",
1158-
parse_pin_names,
1159-
"IncludeCPP:=",
1160-
include_cpp,
1161-
cpp_settings,
1162-
],
1166+
export_circuit_context,
11631167
model,
11641168
frequency,
11651169
)

tests/system/solvers/test_31_Q3D.py

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -483,6 +483,18 @@ def test_equivalent_circuit(self, q3d_solved2):
483483
assert not q3d.export_equivalent_circuit(
484484
output_file=os.path.join(self.local_scratch.path, "test_export_circuit.cir"), setup="Setup1", sweep="Sweep1"
485485
)
486+
487+
assert q3d.export_equivalent_circuit(
488+
output_file=os.path.join(self.local_scratch.path, "test_export_circuit.cir"),
489+
matrix="Original",
490+
cells=1,
491+
include_acr=True,
492+
include_acl=True,
493+
include_cap=True,
494+
include_cond=True,
495+
include_cpp=True,
496+
)
497+
486498
assert q3d.export_equivalent_circuit(
487499
output_file=os.path.join(self.local_scratch.path, "test_export_circuit.cir"), matrix="Original"
488500
)

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