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added create_component_from_spicemodel method in Circuit (#947)
* added create_component_from_spicemodel method in Circuit * added create_component_from_spicemodel method in Circuit * added create_component_from_spicemodel method in Circuit * added create_component_from_spicemodel method in Circuit * added create_component_from_spicemodel method in Circuit Co-authored-by: maxcapodi78 <Shark78>
1 parent 24e022e commit 0d3da45

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6 files changed

+94
-10
lines changed

6 files changed

+94
-10
lines changed

_unittest/conftest.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
test_project_name = "test_primitives"
5050

5151
sys.path.append(local_path)
52-
from .launch_desktop_tests import run_desktop_tests
52+
from _unittest.launch_desktop_tests import run_desktop_tests
5353

5454
# set scratch path and create it if necessary
5555
scratch_path = tempfile.gettempdir()

_unittest/example_models/test.lib

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
*----------------------------------------------------------------------
2+
* PSPICE Model generated by PyAEDT
3+
* Property : C = 0.22 [uF]
4+
*----------------------------------------------------------------------
5+
* Applicable Conditions:
6+
* Frequency Range = 100Hz - 6GHz
7+
* Temperature = -55 degC - 125 degC
8+
* DC Bias Voltage = 0V - 100V
9+
* Small Signal Operation
10+
*----------------------------------------------------------------------
11+
* Encrypted Netlist
12+
*----------------------------------------------------------------------
13+
.subckt GRM1234 Port1 Port2 PARAMS: temperature=25
14+
C1 Port1 Port2 1e-12
15+
.ends
16+
17+
.subckt GRM2345 Port1 Port2
18+
C1 Port1 Port2 1e-12
19+
.ends

_unittest/test_21_Circuit.py

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -320,3 +320,9 @@ def test_28_load_and_save_diff_pair_file(self):
320320
with open(diff_file2, "r") as fh:
321321
lines = fh.read().splitlines()
322322
assert len(lines) == 3
323+
324+
def test_29_create_circuit_from_spice(self):
325+
model = os.path.join(local_path, "example_models", "test.lib")
326+
assert self.aedtapp.modeler.schematic.create_component_from_spicemodel(model)
327+
assert self.aedtapp.modeler.schematic.create_component_from_spicemodel(model, "GRM2345")
328+
assert not self.aedtapp.modeler.schematic.create_component_from_spicemodel(model, "GRM2346")

pyaedt/circuit.py

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,11 @@ def create_schematic_from_netlist(self, file_to_import):
264264
already_exist = True
265265
if not already_exist:
266266
self.modeler.schematic.create_new_component_from_symbol(
267-
parameter, pins, fields[0][0], parameter_list, parameter_value
267+
parameter,
268+
pins,
269+
refbase=fields[0][0],
270+
parameter_list=parameter_list,
271+
parameter_value=parameter_value,
268272
)
269273
mycomp = self.modeler.schematic.create_component(
270274
fields[0],
@@ -295,7 +299,11 @@ def create_schematic_from_netlist(self, file_to_import):
295299
already_exist = True
296300
if not already_exist:
297301
self.modeler.schematic.create_new_component_from_symbol(
298-
parameter, pins, fields[0][0], parameter_list, parameter_value
302+
parameter,
303+
pins,
304+
refbase=fields[0][0],
305+
parameter_list=parameter_list,
306+
parameter_value=parameter_value,
299307
)
300308
mycomp = self.modeler.schematic.create_component(
301309
fields[0],

pyaedt/modeler/PrimitivesNexxim.py

Lines changed: 57 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
import os
2+
import re
23
import warnings
34

45
from pyaedt.generic.general_methods import generate_unique_name
@@ -928,7 +929,7 @@ def create_new_component_from_symbol(
928929
pin_lists,
929930
time_stamp=1591858313,
930931
description="",
931-
refbase="U",
932+
refbase="x",
932933
parameter_list=[],
933934
parameter_value=[],
934935
gref="",
@@ -1032,13 +1033,12 @@ def create_new_component_from_symbol(
10321033
arg2 = ["NAME:Parameters"]
10331034

10341035
for el, val in zip(parameter_list, parameter_value):
1035-
if isinstance(val, str):
1036+
if "MOD" in el:
10361037
arg2.append("TextValueProp:=")
10371038
arg2.append([el, "D", "", val])
1038-
10391039
else:
1040-
arg2.append("ValueProp:=")
1041-
arg2.append([el, "D", "", str(val), False, ""])
1040+
arg2.append("ValuePropNU:=")
1041+
arg2.append([el, "D", "", str(val), 0, ""])
10421042

10431043
arg2.append("ButtonProp:=")
10441044
arg2.append(["CosimDefinition", "D", "", "Edit", "Edit", 40501, "ButtonPropClientData:=", []])
@@ -1051,7 +1051,7 @@ def create_new_component_from_symbol(
10511051
while id < len(pin_lists):
10521052
spicesintax += "%" + str(id) + " "
10531053
id += 1
1054-
spicesintax += symbol_name + " "
1054+
# spicesintax += symbol_name + " "
10551055
for el, val in zip(parameter_list, parameter_value):
10561056
if "MOD" in el:
10571057
spicesintax += "@{} ".format(el)
@@ -1750,3 +1750,54 @@ def assign_sin_excitation2ports(self, ports, settings):
17501750
DeprecationWarning,
17511751
)
17521752
return self._app.assign_voltage_sinusoidal_excitation_to_ports(ports, settings)
1753+
1754+
@pyaedt_function_handler()
1755+
def _parse_spice_model(self, model_path):
1756+
models = []
1757+
with open(model_path, "r") as f:
1758+
for line in f:
1759+
if ".subckt" in line.lower():
1760+
pinNames = [i.strip() for i in re.split(" |\t", line) if i]
1761+
models.append(pinNames[1])
1762+
return models
1763+
1764+
@pyaedt_function_handler()
1765+
def create_component_from_spicemodel(self, model_path, model_name=None, location=None):
1766+
"""Create and place a new component based on a spice .lib file.
1767+
1768+
Parameters
1769+
----------
1770+
model_path : str
1771+
Path to .lib file.
1772+
model_name : str, optional
1773+
Model name to import. If `None` the first subckt in the lib file will be placed.
1774+
location : list, optional
1775+
Position in the schematic of the new component.
1776+
1777+
Returns
1778+
-------
1779+
:class:`pyaedt.modeler.Object3d.CircuitComponent`
1780+
Circuit Component Object.
1781+
"""
1782+
models = self._parse_spice_model(model_path)
1783+
if not model_name and models:
1784+
model_name = models[0]
1785+
elif model_name not in models:
1786+
return False
1787+
arg = ["NAME:Options", "Mode:=", 2, "Overwrite:=", False, "SupportsSimModels:=", False, "LoadOnly:=", False]
1788+
arg2 = ["NAME:Models"]
1789+
for el in models:
1790+
arg2.append(el + ":=")
1791+
if el == model_name:
1792+
arg2.append([True, "", "", False])
1793+
else:
1794+
arg2.append([False, "", "", False])
1795+
arg.append(arg2)
1796+
self.o_component_manager.ImportModelsFromFile(model_path, arg)
1797+
1798+
return self.create_component(
1799+
None,
1800+
component_library=None,
1801+
component_name=model_name,
1802+
location=location,
1803+
)

requirements_test.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
pyvista
22
matplotlib
33
numpy
4-
pytest
4+
pytest==7.0.0
55
pytest-cov
66
codecov

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