Merge pull request #316 from yrabbit/clkdiv-clkdiv2

Implement CLKDIV2 and CLKDIV for all boards.

Author: yrabbit

apycula/chipdb.py

@@ -177,16 +177,26 @@ def bank_tiles(self):
 # If suddenly a command is given to assign an already used wire to another
 # node, then all the contents of this node are combined with the existing one,
 # and the node itself is destroyed.
+# To prevent further attempts to add wires to the destroyed node, we return the
+# name of the node to which the connection was made
 wire2node = {}
 def add_node(dev, node_name, wire_type, row, col, wire):
     if (row, col, wire) not in wire2node:
         wire2node[row, col, wire] = node_name
         dev.nodes.setdefault(node_name, (wire_type, set()))[1].add((row, col, wire))
+        return node_name
     else:
-        if node_name != wire2node[row, col, wire] and node_name in dev.nodes:
-            #print(f'{node_name} -> {wire2node[row, col, wire]} share ({row}, {col}, {wire})')
-            dev.nodes[wire2node[row, col, wire]][1].update(dev.nodes[node_name][1])
-            del dev.nodes[node_name]
+        old_node_name = wire2node[row, col, wire]
+        if node_name != old_node_name:
+            if node_name in dev.nodes:
+                #print(f'#0 {node_name} -> {wire2node[row, col, wire]} share ({row}, {col}, {wire})')
+                dev.nodes[old_node_name][1].update(dev.nodes[node_name][1])
+                del dev.nodes[node_name]
+            else:
+                #print(f'#1 {node_name} -> {wire2node[row, col, wire]} share ({row}, {col}, {wire})')
+                dev.nodes[old_node_name][1].add((row, col, wire))
+        return old_node_name
+    return node_name
 
 # create bels for entry potints to the global clock nets
 def add_buf_bel(dev, row, col, wire, buf_type = 'BUFG'):
@@ -1036,6 +1046,24 @@ def fse_create_hclk_aliases(db, device, dat: Datfile):
             1: HCLK_PINS((27,0), [("CALIB",27,0,"C5"), ("RESETN",27,0,"B5") ], [("RESETN",27,0,"A1") ], [("RESETN",27,0,"C1")])
         }
     },
+    "GW1N-9": {
+        "TOPSIDE":{
+            0: HCLK_PINS((0,0), [("CALIB",9,0,"A2"), ("RESETN",9,0,"B0")], [("RESETN",9,0,"B2")], [("RESETN",9,0,"B4")]),
+            1: HCLK_PINS((0,46), [("CALIB",9,0,"A3"), ("RESETN",9,0,"B1")], [("RESETN",9,0,"B3")], [("RESETN",9,0,"B5")])
+        },
+        "RIGHTSIDE":{
+            0: HCLK_PINS((18,46), [("CALIB",18,46,"A2"), ("RESETN",18,46,"B0")], [("RESETN",18,46,"B2")], [("RESETN",18,46,"B4")]),
+            1: HCLK_PINS((18,46), [("CALIB",18,46,"A3"), ("RESETN",18,46,"B1")], [("RESETN",18,46,"B3")], [("RESETN",18,46,"B5")])
+        },
+        "BOTTOMSIDE":{
+            0: HCLK_PINS((28,0), [("CALIB",28,0,"D0"), ("RESETN",28,0,"D2")], [("RESETN",28,0,"D4")], [("RESETN",28,0,"C0")]),
+            1: HCLK_PINS((28,46), [("CALIB",28,0,"D1"), ("RESETN",28,0,"D3")], [("RESETN",28,0,"D5")], [("RESETN",28,0,"C1")])
+        },
+        "LEFTSIDE":{
+            0: HCLK_PINS((18,0), [("CALIB",18,0,"A2"), ("RESETN",18,0,"B0") ], [("RESETN",18,0,"B2") ], [("RESETN",18,0,"B4") ]),
+            1: HCLK_PINS((18,0), [("CALIB",18,0,"A3"), ("RESETN",18,0,"B1") ], [("RESETN",18,0,"B3") ], [("RESETN",18,0,"B5") ])
+        }
+    },
     "GW1N-9C": {
         "TOPSIDE":{
             0: HCLK_PINS((0,0), [("CALIB",9,0,"A2"), ("RESETN",9,0,"B0")], [("RESETN",9,0,"B2")], [("RESETN",9,0,"B4")]),
@@ -1053,7 +1081,51 @@ def fse_create_hclk_aliases(db, device, dat: Datfile):
             0: HCLK_PINS((18,0), [("CALIB",18,0,"A2"), ("RESETN",18,0,"B0") ], [("RESETN",18,0,"B2") ], [("RESETN",18,0,"B4") ]),
             1: HCLK_PINS((18,0), [("CALIB",18,0,"A3"), ("RESETN",18,0,"B1") ], [("RESETN",18,0,"B3") ], [("RESETN",18,0,"B5") ])
         }
-    }
+    },
+    "GW1N-1": {
+        "BOTTOMSIDE":{
+            0: HCLK_PINS((10, 0), [("CALIB", 10, 0, "D2"), ("RESETN", 10, 0, "D0")], [("RESETN", 10, 0, "D4")], [("RESETN", 10, 0, "D6")]),
+            1: HCLK_PINS((10, 19), [("CALIB", 10, 0, "D3"), ("RESETN", 10, 0, "D1")], [("RESETN", 10, 0, "D5")], [("RESETN", 10, 0, "D7")])
+        },
+    },
+    "GW1NZ-1": {
+        "TOPSIDE":{
+            0: HCLK_PINS((0, 5), [("CALIB", 0, 19, "D3"), ("RESETN", 0, 19, "D1")], [("RESETN", 0, 18, "C2")], [("RESETN", 0, 18, "C4")]),
+            1: HCLK_PINS((0, 5), [("CALIB", 0, 19, "D2"), ("RESETN", 0, 19, "D0")], [("RESETN", 0, 18, "C3")], [("RESETN", 0, 18, "C5")])
+        },
+        "RIGHTSIDE":{
+            0: HCLK_PINS((5, 19), [("CALIB", 10, 19, "D3"), ("RESETN", 10, 19, "D1")], [("RESETN", 10, 18, "C2")], [("RESETN", 10, 18, "C4")]),
+            1: HCLK_PINS((5, 19), [("CALIB", 10, 19, "D2"), ("RESETN", 10, 19, "D1")], [("RESETN", 10, 18, "C3")], [("RESETN", 10, 18, "C5")])
+        },
+    },
+    "GW1NS-4": {
+        "TOPSIDE":{
+            0: HCLK_PINS((0, 18), [("CALIB", 1, 0, "C0"), ("RESETN", 0, 0, "C5")], [("RESETN", 0, 0, "B1")], [("RESETN", 1, 0, "C6")]),
+            1: HCLK_PINS((0, 18), [("CALIB", 1, 0, "D7"), ("RESETN", 0, 0, "B0")], [("RESETN", 1, 0, "C7")], [("RESETN", 1, 0, "C5")])
+        },
+        "RIGHTSIDE":{
+            0: HCLK_PINS((9, 37), [("CALIB", 0, 37, "D7"), ("RESETN", 0, 37, "D5")], [("RESETN", 0, 37, "C3")], [("RESETN", 0, 37, "C1")]),
+            1: HCLK_PINS((9, 37), [("CALIB", 0, 37, "D6"), ("RESETN", 0, 37, "D6")], [("RESETN", 0, 37, "C2")], [("RESETN", 0, 37, "C0")])
+        },
+        "BOTTOMSIDE":{
+            0: HCLK_PINS((19, 16), [("CALIB", 19, 0, "D0"), ("RESETN", 19, 0, "D2")], [("RESETN", 19, 0, "D4")], [("RESETN", 19, 0, "C0")]),
+            1: HCLK_PINS((19, 17), [("CALIB", 19, 0, "D1"), ("RESETN", 19, 0, "D3")], [("RESETN", 19, 0, "D5")], [("RESETN", 19, 0, "C1")])
+        },
+    },
+    "GW1N-4": {
+        "LEFTSIDE":{
+            0: HCLK_PINS((9, 0), [("CALIB", 19, 0,"B4"), ("RESETN", 19, 0, "B6") ], [("RESETN", 19, 0, "A0")], [("RESETN", 19, 0, "A2")]),
+            1: HCLK_PINS((9 ,0), [("CALIB", 19, 0,"B5"), ("RESETN", 19, 0, "B7") ], [("RESETN", 19, 0, "A1")], [("RESETN", 19, 0, "A3")])
+        },
+        "RIGHTSIDE":{
+            0: HCLK_PINS((9, 37), [("CALIB", 0, 37, "B7"), ("RESETN", 0, 37, "B5")], [("RESETN", 0, 37, "C3")], [("RESETN", 0, 37, "C1")]),
+            1: HCLK_PINS((9, 37), [("CALIB", 0, 37, "B6"), ("RESETN", 0, 37, "B6")], [("RESETN", 0, 37, "C2")], [("RESETN", 0, 37, "C0")])
+        },
+        "BOTTOMSIDE":{
+            0: HCLK_PINS((19, 0),  [("CALIB", 19, 0, "D0"), ("RESETN", 19, 0, "D2")], [("RESETN", 19, 0, "D4")], [("RESETN", 19, 0, "C0")]),
+            1: HCLK_PINS((19, 37), [("CALIB", 19, 0, "D1"), ("RESETN", 19, 0, "D3")], [("RESETN", 19, 0, "D5")], [("RESETN", 19, 0, "C1")])
+        },
+    },
 }
 
 
@@ -1075,7 +1147,7 @@ def _iter_edge_coords(dev):
 
 def add_hclk_bels(dat, dev, device):
     #Stub for parts that don't have HCLK bel support yet
-    if device not in ("GW2A-18", "GW2A-18C", "GW1N-9C"):
+    if device not in ("GW2A-18", "GW2A-18C", "GW1N-9", "GW1N-9C", "GW1N-1", "GW1NZ-1", "GW1NS-4", "GW1N-4"):
         to_connect = ['HCLK0_SECT0_IN', 'HCLK0_SECT1_IN', 'HCLK1_SECT0_IN', 'HCLK1_SECT1_IN']
         for x in range(dev.cols):
             for y in range(dev.rows):
@@ -1092,6 +1164,22 @@ def add_hclk_bels(dat, dev, device):
         device = "GW2A-18"
     device_hclk_pins = _device_hclk_pin_dict[device]
 
+    if device == 'GW1NS-4':
+        node_name = 'X16Y19/HCLK0_SECT0_IN'
+        node_name = add_node(dev, node_name, 'HCLK', 19, 16, 'HCLK0_SECT0_IN')
+        node_name = add_node(dev, node_name, 'HCLK', 19, 17, 'HCLK0_SECT0_IN')
+        node_name = 'X17Y19/HCLK1_SECT0_IN'
+        node_name = add_node(dev, node_name, 'HCLK', 19, 17, 'HCLK1_SECT0_IN')
+        node_name = add_node(dev, node_name, 'HCLK', 19, 20, 'HCLK1_SECT0_IN')
+        node_name = 'X17Y19/HCLK1_SECT1_IN'
+        node_name = add_node(dev, node_name, 'HCLK', 19, 17, 'HCLK1_SECT1_IN')
+        node_name = add_node(dev, node_name, 'HCLK', 19, 20, 'HCLK1_SECT1_IN')
+        node_name = 'X17Y19/HCLK_IN2'
+        node_name = add_node(dev, node_name, 'HCLK', 19, 17, 'HCLK_IN2')
+        node_name = add_node(dev, node_name, 'HCLK', 19, 20, 'HCLK_IN2')
+        node_name = 'X17Y19/HCLK_IN3'
+        node_name = add_node(dev, node_name, 'HCLK', 19, 17, 'HCLK_IN3')
+        add_node(dev, node_name, 'HCLK', 19, 20, 'HCLK_IN3')
 
     #There is a sleight of hand going on here - there is likely only one physical CLKDIV bel per HCLK
     #However because of how they are connected, and how I suspect that the muxes that utilize them are,
@@ -1132,7 +1220,7 @@ def add_hclk_bels(dat, dev, device):
                 dev.grid[tile_row][tile_col].bels[clkdiv2_name] = clkdiv2
                 dev.grid[tile_row][tile_col].bels[clkdiv_name] = clkdiv #We still create this so as not to break the PnR logic
 
-                if device in ("GW1N-9C, GW1NR-9C"):
+                if device == "GW1N-9C":
                     clkdiv2_in = f"HCLK{idx}_SECT{section}_IN" if section==0 else f"HCLK_IN{idx*2+section}"
                     dev.hclk_pips[tile_row,tile_col][clkdiv2.portmap["HCLKIN"]] = {clkdiv2_in:set()}
                     sect_div2_mux = f"HCLK{idx}_SECT{section}_MUX_DIV2"
@@ -1150,7 +1238,6 @@ def add_hclk_bels(dat, dev, device):
 
                 else:
                     dev.hclk_pips[tile_row,tile_col][clkdiv2.portmap["HCLKIN"]] = {f"HCLK{idx}_SECT{section}_IN":set()}
-                    # sect_div2_mux = f"HCLK{idx}_SECT{section}_MUX_DIV2"
                     sect_div2_mux = f"HCLK{idx}_SECT{section}_MUX2"
                     dev.hclk_pips[tile_row,tile_col][sect_div2_mux] = {f"HCLK{idx}_SECT{section}_IN":set(), clkdiv2.portmap["CLKOUT"]:set()}
                     dev.hclk_pips[tile_row,tile_col][clkdiv.portmap["HCLKIN"]] = ({sect_div2_mux:set()})
@@ -1204,7 +1291,8 @@ def fse_create_hclk_nodes(dev, device, fse, dat: Datfile):
                             add_node(dev, f'HCLKMUX{src[-1]}', "GLOBAL_CLK", row, col, src)
                 # strange GW1N-9C input-input aliases
                 for i in {0, 2}:
-                    dev.nodes.setdefault(f'X{col}Y{row}/HCLK9-{i}', ('HCLK', {(row, col, f'HCLK_IN{i}')}))[1].add((row, col, f'HCLK_9IN{i}'))
+                    add_node(dev, f'X{col}Y{row}/HCLK9-{i}', 'HCLK', row, col, f'HCLK_IN{i}')
+                    add_node(dev, f'X{col}Y{row}/HCLK9-{i}', 'HCLK', row, col, f'HCLK_9IN{i}')
                 # GW1N-9C clock pin aliases
                 if side != 'B': # it’s still unclear on this side, but the
                                 # Tangnano9k external clock is not connected here, so we

apycula/gowin_pack.py

@@ -81,6 +81,17 @@ def extra_pll_bels(cell, row, col, num, cellname):
             yield ('RPLLB', int(row), int(col) + offx * off, num,
                 cell['parameters'], cell['attributes'], sanitize_name(cellname) + f'B{off}', cell)
 
+def extra_clkdiv_bels(cell, row, col, num, cellname):
+    if device in {'GW1NS-4'}:
+        if int(col) == 18:
+            bel_type = f'{cell["type"]}_AUX'
+            yield (bel_type, int(row), int(col) + 3, num,
+                cell['parameters'], cell['attributes'], sanitize_name(cellname) + 'AUX', cell)
+        if int(col) == 17:
+            bel_type = f'{cell["type"]}_AUX'
+            yield (bel_type, int(row), int(col) + 1, num,
+                cell['parameters'], cell['attributes'], sanitize_name(cellname) + 'AUX', cell)
+
 def extra_mipi_bels(cell, row, col, num, cellname):
     yield ('MIPI_IBUF_AUX', int(row), int(col) + 1, num,
         cell['parameters'], cell['attributes'], sanitize_name(cellname) + 'AUX', cell)
@@ -184,6 +195,7 @@ def get_bits(init_data):
             x0 += 1
         y += 1
 
+_clkdiv_cell_types = {'CLKDIV', 'CLKDIV2'}
 _bsram_cell_types = {'DP', 'SDP', 'SP', 'ROM'}
 _dsp_cell_types = {'ALU54D', 'MULT36X36', 'MULTALU36X18', 'MULTADDALU18X18', 'MULTALU18X18', 'MULT18X18', 'MULT9X9', 'PADD18', 'PADD9'}
 def get_bels(data):
@@ -220,6 +232,8 @@ def get_bels(data):
         if cell_type == 'rPLL':
             cell_type = 'RPLLA'
             yield from extra_pll_bels(cell, row, col, num, cellname)
+        if cell_type in _clkdiv_cell_types:
+            yield from extra_clkdiv_bels(cell, row, col, num, cellname)
         if cell_type in _bsram_cell_types:
             yield from extra_bsram_bels(cell, row, col, num, cellname)
         if cell_type in _dsp_cell_types:
@@ -2063,10 +2077,9 @@ def set_hclk_attrs(db, params, num, typ, cell_name):
             raise Exception(f"Invalid DIV_MODE {bin_match or params['DIV_MODE']} for CLKDIV {cell_name} on device {device}")
         params["DIV_MODE"] = str(bin_match[0])
 
-
-    if (typ == "CLKDIV2"):
+    if typ.startswith("CLKDIV2"):
         attrs[f"BK{section_idx}MUX{hclk_idx}_OUTSEL"] = "DIV2"
-    elif (typ == "CLKDIV"):
+    elif typ.startswith("CLKDIV"):
         attrs[f"HCLKDIV{hclk_idx}_DIV"] = params["DIV_MODE"]
         if (section_idx == '1'):
             attrs[f"HCLKDCS{hclk_idx}_SEL"] = f"HCLKBK{section_idx}{hclk_idx}"
@@ -2608,7 +2621,7 @@ def place(db, tilemap, bels, cst, args):
             # for the corresponding HCLK and set its fuses.
             _, wire, _, side = db.extra_func[row - 1, col -1]['dhcen'][int(num)]['pip']
             hclk_attrs = find_and_set_dhcen_hclk_fuses(db, tilemap, wire, side)
-        elif typ in ["CLKDIV", "CLKDIV2"]:
+        elif typ.startswith("CLKDIV"):
             hclk_attrs = set_hclk_attrs(db, parms, num, typ, cellname)
             bits = get_shortval_fuses(db, tiledata.ttyp, hclk_attrs, "HCLK")
             for r, c in bits:

apycula/gowin_unpack.py

@@ -333,6 +333,11 @@ def parse_tile_(db, row, col, tile, default=True, noalias=False, noiostd = True)
     skip_bels = set()
     #print((row, col))
     tiledata = db.grid[row][col]
+    #if 'HCLK' in db.shortval[tiledata.ttyp].keys():
+    #    attrvals =parse_attrvals(tile, db.logicinfo['HCLK'], db.shortval[tiledata.ttyp]['HCLK'], attrids.hclk_attrids)
+    #    if attrvals:
+    #        print(row, col, attrvals)
+
     clock_pips = {}
     bels = {}
     for name, bel in tiledata.bels.items():