Merge pull request #254 from yrabbit/bsram-doc-3

BSRAM BLKSEL fix

Author: yrabbit

apycula/chipdb.py

@@ -1656,6 +1656,8 @@ def set_chip_flags(dev, device):
         dev.chip_flags.append("NEED_SP_FIX")
     if device in {'GW1N-9C', 'GW2A-18C'}:
         dev.chip_flags.append("NEED_BSRAM_OUTREG_FIX")
+    if device in {'GW1N-1', 'GW1NZ-1', 'GW1NS-2', 'GW1N-4', 'GW1NS-4', 'GW1N-9', 'GW1N-9C', 'GW2A-18', 'GW2A-18C'}:
+        dev.chip_flags.append("NEED_BLKSEL_FIX")
 
 def from_fse(device, fse, dat: Datfile):
     dev = Device()

doc/bsram-fix.md

@@ -40,15 +40,21 @@ One more note for the future - if these additional things are intended to correc
 
 ![READ_MODE=1'b0, WRITE_MODE=2'b10](fig/sp-rmode-1-wmode-10.png)
 
-<<<<<<< HEAD
-
 ### Tangnano9k and Tangnano20k
 For chips on these boards, no new elements are formed around the BSRAM, that is, we can conclude that whatever was broken in the previous families was fixed here. However, now the built-in output registers only work with 32 or 36 bits - with a different bit size, the internal registers are disabled (read mode is forced to switch to 1'b0 bypass) and external DFFs are added.
 
 Which type is added, DFFCE or DFFRE, is determined by the SYNC parameter.
 
 ![Tangnano9k and Tangnano20k with READ_MODE=1'b1](fig/sp-rmode-1-9c-20c.png)
 
+### BSRAM block selection
+It seems that block selection using the `BLKSEL[2:0]` signals does not work as expected because the images generated by the Gowin IDE show an interesting re-communication of these signals.
+
+The principle is this: instead of using the `BLKSEL[2:0]` ports, we connect them to constants, thereby making the BSRAM block statically selected, but add a LUT-based `BLKSEL[2:0]` signal decoder that manipulates the Clock Enable port. Of course, the decoder uses only dynamically changing `BLKSEL` networks - there’s no point in bothering with constant bits.
+
+Here is an example of two blocks with a simple decoder:
+![LUT2 decoder](fig/sp-blksel.png)
+
 
 # TODO
   - Explore DPB, SDPB and pROM