Typo in python logic for i32x4.dot_i8x16_i7x16_add_s?

[kripken]

The loop before last there says

  for i in range(0, 8, 2):
    dst[i/4] = tmp[i] + tmp[i+1]

That means it operates on dst[0], dst[0.5], dst[1], dst[1.5]. Should the i/4 be i/2 perhaps?

I tried to compare this to the spec, but See the modified spec for details on the readme has a broken link. And I can't seem to find this relaxed SIMD instruction in the published current wasm spec (was it merged?)

[tlively]

The rendered spec for this instruction can be found at the spectec repo: https://wasm-dsl.github.io/spectec/core/exec/numerics.html#xref-syntax-instructions-syntax-vextternop-mathit-vextternop-mathit-sh-1-mathit-sh-2-c-1-c-2-c-3