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19 | 19 | * - SSE4.2
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20 | 20 | * - AVX
|
21 | 21 | * - AVX2
|
22 |
| - * - AVX512 |
23 | 22 | *
|
24 | 23 | * ARM:
|
25 | 24 | * - NEON
|
|
93 | 92 | #define CCMATH_HAS_SIMD_AVX2 1
|
94 | 93 | #endif
|
95 | 94 |
|
96 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Byte and Word instructions. |
97 |
| - #if defined(__AVX512BW__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512BW) |
98 |
| - #ifndef CCMATH_HAS_SIMD |
99 |
| - #define CCMATH_HAS_SIMD 1 |
100 |
| - #endif |
101 |
| - #define CCMATH_HAS_SIMD_AVX512BW 1 |
102 |
| - #endif |
103 |
| - |
104 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Conflict Detection instructions. |
105 |
| - #if defined(__AVX512CD__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512CD) |
106 |
| - #ifndef CCMATH_HAS_SIMD |
107 |
| - #define CCMATH_HAS_SIMD 1 |
108 |
| - #endif |
109 |
| - #define CCMATH_HAS_SIMD_AVX512CD 1 |
110 |
| - #endif |
111 |
| - |
112 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Doubleword and Quadword instructions. |
113 |
| - #if defined(__AVX512DQ__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512DQ) |
114 |
| - #ifndef CCMATH_HAS_SIMD |
115 |
| - #define CCMATH_HAS_SIMD 1 |
116 |
| - #endif |
117 |
| - #define CCMATH_HAS_SIMD_AVX512DQ 1 |
118 |
| - #endif |
119 |
| - |
120 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Exponential and Reciprocal instructions. |
121 |
| - #if defined(__AVX512ER__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512ER) |
122 |
| - #ifndef CCMATH_HAS_SIMD |
123 |
| - #define CCMATH_HAS_SIMD 1 |
124 |
| - #endif |
125 |
| - #define CCMATH_HAS_SIMD_AVX512ER 1 |
126 |
| - #endif |
127 |
| - |
128 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Foundation instructions. |
129 |
| - #if defined(__AVX512F__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512F) |
130 |
| - #ifndef CCMATH_HAS_SIMD |
131 |
| - #define CCMATH_HAS_SIMD 1 |
132 |
| - #endif |
133 |
| - #define CCMATH_HAS_SIMD_AVX512F 1 |
134 |
| - #endif |
135 |
| - |
136 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Prefetch instructions. |
137 |
| - #if defined(__AVX512PF__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512PF) |
138 |
| - #ifndef CCMATH_HAS_SIMD |
139 |
| - #define CCMATH_HAS_SIMD 1 |
140 |
| - #endif |
141 |
| - #define CCMATH_HAS_SIMD_AVX512PF 1 |
142 |
| - #endif |
143 |
| - |
144 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Vector Length extensions. |
145 |
| - #if defined(__AVX512VL__) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512VL) |
146 |
| - #ifndef CCMATH_HAS_SIMD |
147 |
| - #define CCMATH_HAS_SIMD 1 |
148 |
| - #endif |
149 |
| - #define CCMATH_HAS_SIMD_AVX512VL 1 |
150 |
| - #endif |
151 |
| - |
152 |
| - // Processors that support Intel Advanced Vector Extensions 512 (Intel AVX-512) Byte and Word instructions. |
153 |
| - #if (defined(__AVX512F__) && defined(__AVX512VL__) && defined(__AVX512BW__) && defined(__AVX512DQ__)) || defined(CCM_CONFIG_RT_SIMD_HAS_AVX512) |
154 |
| - #ifndef CCMATH_HAS_SIMD |
155 |
| - #define CCMATH_HAS_SIMD 1 |
156 |
| - #endif |
157 |
| - #define CCMATH_HAS_SIMD_AVX512 1 |
158 |
| - #endif |
159 |
| - |
160 |
| -// Intel Short Vector Math Library (SVML) |
| 95 | +// FMA (Fused Multiply-Add) Extensions |
161 | 96 | #if defined(__FMA__) || defined(CCM_CONFIG_RT_SIMD_HAS_FMA)
|
162 | 97 | #ifndef CCMATH_HAS_SIMD
|
163 | 98 | #define CCMATH_HAS_SIMD 1
|
|
166 | 101 | #endif
|
167 | 102 |
|
168 | 103 | // Intel Short Vector Math Library (SVML)
|
| 104 | +// As far as I am aware, there is no reliable way to detect SVML support at compile-time. |
169 | 105 | #if defined(CCM_CONFIG_RT_SIMD_HAS_SVML)
|
170 | 106 | #ifndef CCMATH_HAS_SIMD
|
171 | 107 | #define CCMATH_HAS_SIMD 1
|
|
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