Fix classical bit mapping in HLS pass (#14597) (#14624)

* Map classical bits from block to outer circuit



* Add regression test

* Add reno

* Avoid allocating cargs

Previously the cargs were being written to a Vec<usize> as an
intermediate storage, however we are just returning them directly and
don't need to allocate or change the types. This commit just works with
the slice returned from the interner directly which both simplifies the
code and should also be faster.

---------



(cherry picked from commit 9ec464a)

Co-authored-by: Elena Peña Tapia <[email protected]>
Co-authored-by: Alexander Ivrii <[email protected]>
Co-authored-by: Matthew Treinish <[email protected]>

Author: 4 people

crates/accelerate/src/high_level_synthesis.rs

@@ -477,6 +477,7 @@ fn run_on_circuitdata(
             .iter()
             .map(|q| input_qubits[q.index()])
             .collect::<Vec<usize>>();
+        let op_clbits = input_circuit.get_cargs(inst.clbits);
 
         // Start by handling special operations.
         // In the future, we can also consider other possible optimizations, e.g.:
@@ -629,8 +630,10 @@ fn run_on_circuitdata(
                         .iter()
                         .map(|q| Qubit::new(qubit_map[&q.index()]))
                         .collect();
-                    let inst_outer_clbits: Vec<Clbit> =
-                        inst_inner_clbits.iter().map(|c| Clbit(c.0)).collect();
+                    let inst_outer_clbits: Vec<Clbit> = inst_inner_clbits
+                        .iter()
+                        .map(|c| op_clbits[c.0 as usize])
+                        .collect();
 
                     output_circuit.push_packed_operation(
                         inst_inner.op.clone(),

releasenotes/notes/fix-hls-clbits-6ddf1f8d1542eed2.yaml

@@ -0,0 +1,7 @@
+---
+fixes:
+  - |
+    Fixed a bug in the :class:`.HighLevelSynthesis` pass where, if the circuit contained high level objects
+    with classical registers, these would get mapped to the relative index in the object instead of the
+    corresponding index in the outer circuit. The classical registers are now correctly mapped to the outer 
+    circuit index.

test/python/transpiler/test_high_level_synthesis.py

@@ -2120,6 +2120,48 @@ def test_unroll_with_clbit(self):
 
         self.assertEqual(block, out)
 
+    def test_unroll_with_clbit_mapping(self):
+        """Test unrolling a custom definition that has qubits and clbits
+        that require mapping to the global clbits.
+        Regression test for: https://github.com/Qiskit/qiskit/issues/14569
+        """
+        block = QuantumCircuit(2, 2)
+        block.h(0)
+        block.measure([0, 1], [0, 1])
+
+        circuit = QuantumCircuit(6, 6)
+        circuit.append(block.to_instruction(), [0, 1], [0, 1])
+        circuit.append(block.to_instruction(), [2, 3], [3, 2])
+        circuit.append(block.to_instruction(), [4, 5], [4, 5])
+
+        hls = HighLevelSynthesis(basis_gates=["h", "measure"])
+        out = hls(circuit)
+
+        self.assertEqual(
+            (out.find_bit(out.data[3].qubits[0]).index, out.find_bit(out.data[3].clbits[0]).index),
+            (0, 0),
+        )
+        self.assertEqual(
+            (out.find_bit(out.data[4].qubits[0]).index, out.find_bit(out.data[4].clbits[0]).index),
+            (1, 1),
+        )
+        self.assertEqual(
+            (out.find_bit(out.data[5].qubits[0]).index, out.find_bit(out.data[5].clbits[0]).index),
+            (3, 2),
+        )
+        self.assertEqual(
+            (out.find_bit(out.data[6].qubits[0]).index, out.find_bit(out.data[6].clbits[0]).index),
+            (2, 3),
+        )
+        self.assertEqual(
+            (out.find_bit(out.data[7].qubits[0]).index, out.find_bit(out.data[7].clbits[0]).index),
+            (4, 4),
+        )
+        self.assertEqual(
+            (out.find_bit(out.data[8].qubits[0]).index, out.find_bit(out.data[8].clbits[0]).index),
+            (5, 5),
+        )
+
 
 class TestGate(Gate):
     """Mock one qubit zero param gate."""