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[FIRRTL] Add doNotPrint flag to InstanceOp (llvm#8331)
This flag acts the same as doNotPrint in hardware. When lowering an instance to the hw dialect, copy the doNotPrint attribute over.
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13 files changed

+101
-86
lines changed

13 files changed

+101
-86
lines changed

‎include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td

Lines changed: 46 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -64,61 +64,57 @@ def InstanceOp : HardwareDeclOp<"instance", [
6464
```
6565
}];
6666

67-
let arguments = (ins FlatSymbolRefAttr:$moduleName, StrAttr:$name, NameKindAttr:$nameKind,
68-
DenseBoolArrayAttr:$portDirections, StrArrayAttr:$portNames,
69-
AnnotationArrayAttr:$annotations,
70-
PortAnnotationsAttr:$portAnnotations,
71-
LayerArrayAttr:$layers,
72-
UnitAttr:$lowerToBind,
73-
OptionalAttr<InnerSymAttr>:$inner_sym);
67+
let arguments = (ins FlatSymbolRefAttr:$moduleName, StrAttr:$name,
68+
NameKindAttr:$nameKind, DenseBoolArrayAttr:$portDirections,
69+
StrArrayAttr:$portNames, AnnotationArrayAttr:$annotations,
70+
PortAnnotationsAttr:$portAnnotations, LayerArrayAttr:$layers,
71+
UnitAttr:$lowerToBind, UnitAttr:$doNotPrint,
72+
OptionalAttr<InnerSymAttr>:$inner_sym);
7473

7574
let results = (outs Variadic<AnyType>:$results);
7675

7776
let hasCustomAssemblyFormat = 1;
7877

79-
let builders = [
80-
OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
81-
"::mlir::StringRef":$moduleName,
82-
"::mlir::StringRef":$name,
83-
"::circt::firrtl::NameKindEnum":$nameKind,
84-
"::mlir::ArrayRef<Direction>":$portDirections,
85-
"::mlir::ArrayRef<Attribute>":$portNames,
86-
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
87-
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
88-
CArg<"::mlir::ArrayRef<Attribute>", "{}">:$layers,
89-
CArg<"bool","false">:$lowerToBind,
90-
CArg<"StringAttr", "StringAttr()">:$innerSym)>,
91-
OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
92-
"::mlir::StringRef":$moduleName,
93-
"::mlir::StringRef":$name,
94-
"::circt::firrtl::NameKindEnum":$nameKind,
95-
"::mlir::ArrayRef<Direction>":$portDirections,
96-
"::mlir::ArrayRef<Attribute>":$portNames,
97-
"ArrayRef<Attribute>":$annotations,
98-
"ArrayRef<Attribute>":$portAnnotations,
99-
"::mlir::ArrayRef<Attribute>":$layers,
100-
"bool":$lowerToBind,
101-
"hw::InnerSymAttr":$innerSym)>,
102-
103-
/// Constructor when you have the target module in hand.
104-
OpBuilder<(ins "FModuleLike":$module,
105-
"mlir::StringRef":$name,
106-
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
107-
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
108-
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
109-
CArg<"bool","false">:$lowerToBind,
110-
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>,
111-
112-
/// Constructor when you have a port info list in hand.
113-
OpBuilder<(ins "ArrayRef<PortInfo>":$ports,
114-
"::mlir::StringRef":$moduleName,
115-
"mlir::StringRef":$name,
116-
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
117-
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
118-
CArg<"ArrayRef<Attribute>", "{}">:$layers,
119-
CArg<"bool","false">:$lowerToBind,
120-
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>
121-
];
78+
let builders =
79+
[OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
80+
"::mlir::StringRef":$moduleName, "::mlir::StringRef":$name,
81+
"::circt::firrtl::NameKindEnum":$nameKind,
82+
"::mlir::ArrayRef<Direction>":$portDirections,
83+
"::mlir::ArrayRef<Attribute>":$portNames,
84+
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
85+
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
86+
CArg<"::mlir::ArrayRef<Attribute>", "{}">:$layers,
87+
CArg<"bool", "false">:$lowerToBind,
88+
CArg<"bool", "false">:$doNotPrint,
89+
CArg<"StringAttr", "StringAttr()">:$innerSym)>,
90+
OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
91+
"::mlir::StringRef":$moduleName, "::mlir::StringRef":$name,
92+
"::circt::firrtl::NameKindEnum":$nameKind,
93+
"::mlir::ArrayRef<Direction>":$portDirections,
94+
"::mlir::ArrayRef<Attribute>":$portNames,
95+
"ArrayRef<Attribute>":$annotations,
96+
"ArrayRef<Attribute>":$portAnnotations,
97+
"::mlir::ArrayRef<Attribute>":$layers, "bool":$lowerToBind,
98+
"bool":$doNotPrint, "hw::InnerSymAttr":$innerSym)>,
99+
100+
/// Constructor when you have the target module in hand.
101+
OpBuilder<(ins "FModuleLike":$module, "mlir::StringRef":$name,
102+
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
103+
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
104+
CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
105+
CArg<"bool", "false">:$lowerToBind,
106+
CArg<"bool", "false">:$doNotPrint,
107+
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>,
108+
109+
/// Constructor when you have a port info list in hand.
110+
OpBuilder<(ins "ArrayRef<PortInfo>":$ports,
111+
"::mlir::StringRef":$moduleName, "mlir::StringRef":$name,
112+
CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
113+
CArg<"ArrayRef<Attribute>", "{}">:$annotations,
114+
CArg<"ArrayRef<Attribute>", "{}">:$layers,
115+
CArg<"bool", "false">:$lowerToBind,
116+
CArg<"bool", "false">:$doNotPrint,
117+
CArg<"hw::InnerSymAttr", "hw::InnerSymAttr()">:$innerSym)>];
122118

123119
let extraClassDeclaration = [{
124120
/// Return the port direction for the specified result number.

‎lib/Analysis/FIRRTLInstanceInfo.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -140,10 +140,13 @@ InstanceInfo::InstanceInfo(Operation *op, mlir::AnalysisManager &am) {
140140
attributes.underDut.mergeIn(parentAttrs.underDut);
141141

142142
// Update underLayer.
143-
auto instanceOp = useIt->getInstance();
144-
bool underLayer = (isa<InstanceOp>(instanceOp) &&
145-
cast<InstanceOp>(instanceOp).getLowerToBind()) ||
146-
instanceOp->getParentOfType<LayerBlockOp>();
143+
bool underLayer = false;
144+
if (auto instanceOp = useIt->getInstance<InstanceOp>()) {
145+
if (instanceOp.getLowerToBind() || instanceOp.getDoNotPrint() ||
146+
instanceOp->getParentOfType<LayerBlockOp>())
147+
underLayer = true;
148+
}
149+
147150
if (!isGCCompanion) {
148151
if (underLayer)
149152
attributes.underLayer.mergeIn(true);

‎lib/Conversion/FIRRTLToHW/LowerToHW.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -249,14 +249,13 @@ struct CircuitLoweringState {
249249
// Pre-populate the dutModules member with a list of all modules that are
250250
// determined to be under the DUT.
251251
auto inDUT = [&](igraph::ModuleOpInterface child) {
252-
auto isBind = [](igraph::InstanceRecord *instRec) {
253-
auto inst = instRec->getInstance();
254-
if (auto *finst = dyn_cast<InstanceOp>(&inst))
255-
return finst->getLowerToBind();
252+
auto isPhony = [](igraph::InstanceRecord *instRec) {
253+
if (auto inst = instRec->getInstance<InstanceOp>())
254+
return inst.getLowerToBind() || inst.getDoNotPrint();
256255
return false;
257256
};
258257
if (auto parent = dyn_cast<igraph::ModuleOpInterface>(*dut))
259-
return getInstanceGraph().isAncestor(child, parent, isBind);
258+
return getInstanceGraph().isAncestor(child, parent, isPhony);
260259
return dut == child;
261260
};
262261
circuitOp->walk([&](FModuleLike moduleOp) {
@@ -3459,7 +3458,7 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
34593458
auto newInstance = builder.create<hw::InstanceOp>(
34603459
newModule, oldInstance.getNameAttr(), operands, parameters, innerSym);
34613460

3462-
if (oldInstance.getLowerToBind())
3461+
if (oldInstance.getLowerToBind() || oldInstance.getDoNotPrint())
34633462
newInstance.setDoNotPrintAttr(builder.getUnitAttr());
34643463

34653464
if (newInstance.getInnerSymAttr())

‎lib/Dialect/FIRRTL/FIRRTLOps.cpp

Lines changed: 30 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2217,24 +2217,30 @@ LogicalResult LayerOp::verify() {
22172217
// InstanceOp
22182218
//===----------------------------------------------------------------------===//
22192219

2220-
void InstanceOp::build(
2221-
OpBuilder &builder, OperationState &result, TypeRange resultTypes,
2222-
StringRef moduleName, StringRef name, NameKindEnum nameKind,
2223-
ArrayRef<Direction> portDirections, ArrayRef<Attribute> portNames,
2224-
ArrayRef<Attribute> annotations, ArrayRef<Attribute> portAnnotations,
2225-
ArrayRef<Attribute> layers, bool lowerToBind, StringAttr innerSym) {
2220+
void InstanceOp::build(OpBuilder &builder, OperationState &result,
2221+
TypeRange resultTypes, StringRef moduleName,
2222+
StringRef name, NameKindEnum nameKind,
2223+
ArrayRef<Direction> portDirections,
2224+
ArrayRef<Attribute> portNames,
2225+
ArrayRef<Attribute> annotations,
2226+
ArrayRef<Attribute> portAnnotations,
2227+
ArrayRef<Attribute> layers, bool lowerToBind,
2228+
bool doNotPrint, StringAttr innerSym) {
22262229
build(builder, result, resultTypes, moduleName, name, nameKind,
22272230
portDirections, portNames, annotations, portAnnotations, layers,
2228-
lowerToBind,
2231+
lowerToBind, doNotPrint,
22292232
innerSym ? hw::InnerSymAttr::get(innerSym) : hw::InnerSymAttr());
22302233
}
22312234

2232-
void InstanceOp::build(
2233-
OpBuilder &builder, OperationState &result, TypeRange resultTypes,
2234-
StringRef moduleName, StringRef name, NameKindEnum nameKind,
2235-
ArrayRef<Direction> portDirections, ArrayRef<Attribute> portNames,
2236-
ArrayRef<Attribute> annotations, ArrayRef<Attribute> portAnnotations,
2237-
ArrayRef<Attribute> layers, bool lowerToBind, hw::InnerSymAttr innerSym) {
2235+
void InstanceOp::build(OpBuilder &builder, OperationState &result,
2236+
TypeRange resultTypes, StringRef moduleName,
2237+
StringRef name, NameKindEnum nameKind,
2238+
ArrayRef<Direction> portDirections,
2239+
ArrayRef<Attribute> portNames,
2240+
ArrayRef<Attribute> annotations,
2241+
ArrayRef<Attribute> portAnnotations,
2242+
ArrayRef<Attribute> layers, bool lowerToBind,
2243+
bool doNotPrint, hw::InnerSymAttr innerSym) {
22382244
result.addTypes(resultTypes);
22392245
result.getOrAddProperties<Properties>().setModuleName(
22402246
SymbolRefAttr::get(builder.getContext(), moduleName));
@@ -2250,6 +2256,9 @@ void InstanceOp::build(
22502256
if (lowerToBind)
22512257
result.getOrAddProperties<Properties>().setLowerToBind(
22522258
builder.getUnitAttr());
2259+
if (doNotPrint)
2260+
result.getOrAddProperties<Properties>().setDoNotPrint(
2261+
builder.getUnitAttr());
22532262
if (innerSym)
22542263
result.getOrAddProperties<Properties>().setInnerSym(innerSym);
22552264

@@ -2272,7 +2281,7 @@ void InstanceOp::build(OpBuilder &builder, OperationState &result,
22722281
FModuleLike module, StringRef name,
22732282
NameKindEnum nameKind, ArrayRef<Attribute> annotations,
22742283
ArrayRef<Attribute> portAnnotations, bool lowerToBind,
2275-
hw::InnerSymAttr innerSym) {
2284+
bool doNotPrint, hw::InnerSymAttr innerSym) {
22762285

22772286
// Gather the result types.
22782287
SmallVector<Type> resultTypes;
@@ -2298,15 +2307,15 @@ void InstanceOp::build(OpBuilder &builder, OperationState &result,
22982307
module.getPortDirectionsAttr(), module.getPortNamesAttr(),
22992308
builder.getArrayAttr(annotations), portAnnotationsAttr,
23002309
module.getLayersAttr(), lowerToBind ? builder.getUnitAttr() : UnitAttr(),
2301-
innerSym);
2310+
doNotPrint ? builder.getUnitAttr() : UnitAttr(), innerSym);
23022311
}
23032312

23042313
void InstanceOp::build(OpBuilder &builder, OperationState &odsState,
23052314
ArrayRef<PortInfo> ports, StringRef moduleName,
23062315
StringRef name, NameKindEnum nameKind,
23072316
ArrayRef<Attribute> annotations,
23082317
ArrayRef<Attribute> layers, bool lowerToBind,
2309-
hw::InnerSymAttr innerSym) {
2318+
bool doNotPrint, hw::InnerSymAttr innerSym) {
23102319
// Gather the result types.
23112320
SmallVector<Type> newResultTypes;
23122321
SmallVector<Direction> newPortDirections;
@@ -2321,7 +2330,7 @@ void InstanceOp::build(OpBuilder &builder, OperationState &odsState,
23212330

23222331
return build(builder, odsState, newResultTypes, moduleName, name, nameKind,
23232332
newPortDirections, newPortNames, annotations, newPortAnnotations,
2324-
layers, lowerToBind, innerSym);
2333+
layers, lowerToBind, doNotPrint, innerSym);
23252334
}
23262335

23272336
LogicalResult InstanceOp::verify() {
@@ -2365,7 +2374,8 @@ InstanceOp InstanceOp::erasePorts(OpBuilder &builder,
23652374
auto newOp = builder.create<InstanceOp>(
23662375
getLoc(), newResultTypes, getModuleName(), getName(), getNameKind(),
23672376
newPortDirections, newPortNames, getAnnotations().getValue(),
2368-
newPortAnnotations, getLayers(), getLowerToBind(), getInnerSymAttr());
2377+
newPortAnnotations, getLayers(), getLowerToBind(), getDoNotPrint(),
2378+
getInnerSymAttr());
23692379

23702380
for (unsigned oldIdx = 0, newIdx = 0, numOldPorts = getNumResults();
23712381
oldIdx != numOldPorts; ++oldIdx) {
@@ -2438,7 +2448,8 @@ InstanceOp::cloneAndInsertPorts(ArrayRef<std::pair<unsigned, PortInfo>> ports) {
24382448
return OpBuilder(*this).create<InstanceOp>(
24392449
getLoc(), newPortTypes, getModuleName(), getName(), getNameKind(),
24402450
newPortDirections, newPortNames, getAnnotations().getValue(),
2441-
newPortAnnos, getLayers(), getLowerToBind(), getInnerSymAttr());
2451+
newPortAnnos, getLayers(), getLowerToBind(), getDoNotPrint(),
2452+
getInnerSymAttr());
24422453
}
24432454

24442455
LogicalResult InstanceOp::verifySymbolUses(SymbolTableCollection &symbolTable) {

‎lib/Dialect/FIRRTL/Import/FIRParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4253,7 +4253,7 @@ ParseResult FIRStmtParser::parseInstance() {
42534253
hw::InnerSymAttr sym = {};
42544254
auto result = builder.create<InstanceOp>(
42554255
referencedModule, id, NameKindEnum::InterestingName,
4256-
annotations.getValue(), portAnnotations, false, sym);
4256+
annotations.getValue(), portAnnotations, false, false, sym);
42574257

42584258
// Since we are implicitly unbundling the instance results, we need to keep
42594259
// track of the mapping from bundle fields to results in the unbundledValues

‎lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -969,7 +969,7 @@ void ExtractInstancesPass::groupInstances() {
969969
wrapper.getLoc(), wrapper, wrapperName, NameKindEnum::DroppableName,
970970
ArrayRef<Attribute>{},
971971
/*portAnnotations=*/ArrayRef<Attribute>{}, /*lowerToBind=*/false,
972-
hw::InnerSymAttr::get(wrapperInstName));
972+
/*doNotPrint=*/false, hw::InnerSymAttr::get(wrapperInstName));
973973
unsigned portIdx = 0;
974974
for (auto inst : insts)
975975
for (auto result : inst.getResults())

‎lib/Dialect/FIRRTL/Transforms/InjectDUTHierarchy.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,7 @@ void InjectDUTHierarchy::runOnOperation() {
177177
auto wrapperInst =
178178
b.create<InstanceOp>(b.getUnknownLoc(), wrapper, wrapper.getModuleName(),
179179
NameKindEnum::DroppableName, ArrayRef<Attribute>{},
180-
ArrayRef<Attribute>{}, false,
180+
ArrayRef<Attribute>{}, false, false,
181181
hw::InnerSymAttr::get(b.getStringAttr(
182182
dutNS.newName(wrapper.getModuleName()))));
183183
for (const auto &pair : llvm::enumerate(wrapperInst.getResults())) {

‎lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -671,6 +671,7 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp,
671671
instanceName, NameKindEnum::DroppableName,
672672
/*annotations=*/ArrayRef<Attribute>{},
673673
/*portAnnotations=*/ArrayRef<Attribute>{}, /*lowerToBind=*/true,
674+
/*doNotPrint=*/false,
674675
/*innerSym=*/
675676
(innerSyms.empty() ? hw::InnerSymAttr{}
676677
: hw::InnerSymAttr::get(builder.getStringAttr(

‎lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -497,7 +497,7 @@ InstanceOp LowerMemoryPass::emitMemoryInstance(MemOp op, FModuleOp module,
497497
/*annotations=*/ArrayRef<Attribute>(),
498498
/*portAnnotations=*/ArrayRef<Attribute>(),
499499
/*layers=*/ArrayRef<Attribute>(), /*lowerToBind=*/false,
500-
op.getInnerSymAttr());
500+
/*doNotPrint=*/false, op.getInnerSymAttr());
501501

502502
// Update all users of the result of read ports
503503
for (auto [subfield, result] : returnHolder) {

‎lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -404,7 +404,7 @@ static void lowerModuleBody(FModuleOp mod,
404404
auto newOp = theBuilder.create<InstanceOp>(
405405
instPorts, inst.getModuleName(), inst.getName(), inst.getNameKind(),
406406
annos.getValue(), inst.getLayers(), inst.getLowerToBind(),
407-
inst.getInnerSymAttr());
407+
inst.getDoNotPrint(), inst.getInnerSymAttr());
408408

409409
auto oldDict = inst->getDiscardableAttrDictionary();
410410
auto newDict = newOp->getDiscardableAttrDictionary();

‎lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1508,7 +1508,7 @@ bool TypeLoweringVisitor::visitDecl(InstanceOp op) {
15081508
op.getNameKindAttr(), direction::packAttribute(context, newDirs),
15091509
builder->getArrayAttr(newNames), op.getAnnotations(),
15101510
builder->getArrayAttr(newPortAnno), op.getLayersAttr(),
1511-
op.getLowerToBindAttr(),
1511+
op.getLowerToBindAttr(), op.getDoNotPrintAttr(),
15121512
sym ? hw::InnerSymAttr::get(sym) : hw::InnerSymAttr());
15131513

15141514
newInstance->setDiscardableAttrs(op->getDiscardableAttrDictionary());

‎lib/Dialect/FIRRTL/Transforms/SpecializeOption.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ struct SpecializeOptionPass
8585
inst.getNameKindAttr(), inst.getPortDirectionsAttr(),
8686
inst.getPortNamesAttr(), inst.getAnnotationsAttr(),
8787
inst.getPortAnnotationsAttr(), builder.getArrayAttr({}),
88-
UnitAttr{}, inst.getInnerSymAttr());
88+
UnitAttr{}, UnitAttr{}, inst.getInnerSymAttr());
8989
inst.replaceAllUsesWith(newInst);
9090
inst.erase();
9191

‎test/Conversion/FIRRTLToHW/lower-to-hw.mlir

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -683,6 +683,11 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
683683
firrtl.connect %qux, %dummy : !firrtl.uint<1>, !firrtl.uint<1>
684684
}
685685

686+
// CHECK-LABEL: hw.module @DoNotPrintTest()
687+
firrtl.module @DoNotPrintTest() {
688+
// CHECK: hw.instance "foo" @foo() -> () {doNotPrint}
689+
firrtl.instance foo {doNotPrint} @foo()
690+
}
686691

687692
// CHECK-LABEL: hw.module private @attributes_preservation
688693
// CHECK-SAME: firrtl.foo = "bar"

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