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[RISCV] Match widening fp instructions with same fpext used in multiple operands (llvm#125803)
Because the fpext has a single use constraint on it we can't match cases where it's used for both operands. Introduce a new PatFrag that allows multiple uses on a single user and use it for the binary patterns, and some ternary patterns. (For some of the ternary patterns there is a fneg that counts as a separate user, we still need to handle these)
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6 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

+13-13
Original file line numberDiff line numberDiff line change
@@ -536,19 +536,19 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
536536
defvar wti = vtiToWti.Wti;
537537
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
538538
GetVTypePredicates<wti>.Predicates) in {
539-
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
539+
def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
540540
(vti.Vector vti.RegClass:$rs2),
541541
(vti.Mask true_mask), (XLenVT srcvalue))),
542-
(wti.Vector (riscv_fpextend_vl_oneuse
542+
(wti.Vector (riscv_fpextend_vl_sameuser
543543
(vti.Vector vti.RegClass:$rs1),
544544
(vti.Mask true_mask), (XLenVT srcvalue)))),
545545
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
546546
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
547547
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
548-
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
548+
def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
549549
(vti.Vector vti.RegClass:$rs2),
550550
(vti.Mask true_mask), (XLenVT srcvalue))),
551-
(wti.Vector (riscv_fpextend_vl_oneuse
551+
(wti.Vector (riscv_fpextend_vl_sameuser
552552
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
553553
(vti.Mask true_mask), (XLenVT srcvalue)))),
554554
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -571,10 +571,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
571571
defvar wti = vtiToWti.Wti;
572572
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
573573
GetVTypePredicates<wti>.Predicates) in {
574-
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
574+
def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
575575
(vti.Vector vti.RegClass:$rs2),
576576
(vti.Mask true_mask), (XLenVT srcvalue))),
577-
(wti.Vector (riscv_fpextend_vl_oneuse
577+
(wti.Vector (riscv_fpextend_vl_sameuser
578578
(vti.Vector vti.RegClass:$rs1),
579579
(vti.Mask true_mask), (XLenVT srcvalue)))),
580580
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW)
@@ -584,10 +584,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
584584
// RISCVInsertReadWriteCSR
585585
FRM_DYN,
586586
vti.AVL, vti.Log2SEW, TA_MA)>;
587-
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
587+
def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
588588
(vti.Vector vti.RegClass:$rs2),
589589
(vti.Mask true_mask), (XLenVT srcvalue))),
590-
(wti.Vector (riscv_fpextend_vl_oneuse
590+
(wti.Vector (riscv_fpextend_vl_sameuser
591591
(vti.Vector (SplatFPOp (vti.Scalar vti.ScalarRegClass:$rs1))),
592592
(vti.Mask true_mask), (XLenVT srcvalue)))),
593593
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
@@ -669,10 +669,10 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
669669
!if(!eq(vti.Scalar, bf16),
670670
[HasStdExtZvfbfwma],
671671
[])) in {
672-
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
672+
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_sameuser
673673
(vti.Vector vti.RegClass:$rs1),
674674
(vti.Mask true_mask), (XLenVT srcvalue))),
675-
(wti.Vector (riscv_fpextend_vl_oneuse
675+
(wti.Vector (riscv_fpextend_vl_sameuser
676676
(vti.Vector vti.RegClass:$rs2),
677677
(vti.Mask true_mask), (XLenVT srcvalue))),
678678
(wti.Vector wti.RegClass:$rd)),
@@ -749,11 +749,11 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
749749
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
750750
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
751751
GetVTypePredicates<wti>.Predicates) in {
752-
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
752+
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_sameuser
753753
(vti.Vector vti.RegClass:$rs1),
754754
(vti.Mask true_mask), (XLenVT srcvalue))),
755-
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
756-
(vti.Mask true_mask), (XLenVT srcvalue)),
755+
(riscv_fpextend_vl_sameuser (vti.Vector vti.RegClass:$rs2),
756+
(vti.Mask true_mask), (XLenVT srcvalue)),
757757
(fneg wti.RegClass:$rd)),
758758
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
759759
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

+5
Original file line numberDiff line numberDiff line change
@@ -554,6 +554,11 @@ def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),
554554
return N->hasOneUse();
555555
}]>;
556556

557+
def riscv_fpextend_vl_sameuser : PatFrag<(ops node:$A, node:$B, node:$C),
558+
(riscv_fpextend_vl node:$A, node:$B, node:$C), [{
559+
return !N->use_empty() && all_equal(N->users());
560+
}]>;
561+
557562
def riscv_vfmadd_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
558563
node:$E),
559564
(riscv_vfmadd_vl node:$A, node:$B,

‎llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll

+12
Original file line numberDiff line numberDiff line change
@@ -323,3 +323,15 @@ define <vscale x 8 x double> @vfwadd_wf_nxv8f64_2(<vscale x 8 x double> %va, flo
323323
%vd = fadd <vscale x 8 x double> %va, %splat
324324
ret <vscale x 8 x double> %vd
325325
}
326+
327+
define <vscale x 1 x double> @vfwadd_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
328+
; CHECK-LABEL: vfwadd_vv_nxv1f64_same_op:
329+
; CHECK: # %bb.0:
330+
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
331+
; CHECK-NEXT: vfwadd.vv v9, v8, v8
332+
; CHECK-NEXT: vmv1r.v v8, v9
333+
; CHECK-NEXT: ret
334+
%vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
335+
%vc = fadd <vscale x 1 x double> %vb, %vb
336+
ret <vscale x 1 x double> %vc
337+
}

‎llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll

+25
Original file line numberDiff line numberDiff line change
@@ -1764,3 +1764,28 @@ define <vscale x 8 x double> @vfwnmsac_fv_nxv8f64(<vscale x 8 x double> %va, <vs
17641764
%vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %vf, <vscale x 8 x double> %va)
17651765
ret <vscale x 8 x double> %vg
17661766
}
1767+
1768+
define <vscale x 1 x double> @vfwma_vv_nxv1f64_same_op(<vscale x 1 x float> %va, <vscale x 1 x double> %vb) {
1769+
; CHECK-LABEL: vfwma_vv_nxv1f64_same_op:
1770+
; CHECK: # %bb.0:
1771+
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
1772+
; CHECK-NEXT: vfwmacc.vv v9, v8, v8
1773+
; CHECK-NEXT: vmv1r.v v8, v9
1774+
; CHECK-NEXT: ret
1775+
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
1776+
%vd = call <vscale x 1 x double> @llvm.fma(<vscale x 1 x double> %vc, <vscale x 1 x double> %vc, <vscale x 1 x double> %vb)
1777+
ret <vscale x 1 x double> %vd
1778+
}
1779+
1780+
define <vscale x 1 x double> @vfwmsac_vv_nxv1f64_same_op(<vscale x 1 x float> %va, <vscale x 1 x double> %vb) {
1781+
; CHECK-LABEL: vfwmsac_vv_nxv1f64_same_op:
1782+
; CHECK: # %bb.0:
1783+
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
1784+
; CHECK-NEXT: vfwmsac.vv v9, v8, v8
1785+
; CHECK-NEXT: vmv1r.v v8, v9
1786+
; CHECK-NEXT: ret
1787+
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
1788+
%vd = fneg <vscale x 1 x double> %vb
1789+
%ve = call <vscale x 1 x double> @llvm.fma(<vscale x 1 x double> %vc, <vscale x 1 x double> %vc, <vscale x 1 x double> %vd)
1790+
ret <vscale x 1 x double> %ve
1791+
}

‎llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll

+12
Original file line numberDiff line numberDiff line change
@@ -175,3 +175,15 @@ define <vscale x 8 x double> @vfwmul_vf_nxv8f64_2(<vscale x 8 x float> %va, floa
175175
%ve = fmul <vscale x 8 x double> %vc, %splat
176176
ret <vscale x 8 x double> %ve
177177
}
178+
179+
define <vscale x 1 x double> @vfwmul_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
180+
; CHECK-LABEL: vfwmul_vv_nxv1f64_same_op:
181+
; CHECK: # %bb.0:
182+
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
183+
; CHECK-NEXT: vfwmul.vv v9, v8, v8
184+
; CHECK-NEXT: vmv1r.v v8, v9
185+
; CHECK-NEXT: ret
186+
%vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
187+
%vc = fmul <vscale x 1 x double> %vb, %vb
188+
ret <vscale x 1 x double> %vc
189+
}

‎llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll

+12
Original file line numberDiff line numberDiff line change
@@ -323,3 +323,15 @@ define <vscale x 8 x double> @vfwsub_wf_nxv8f64_2(<vscale x 8 x double> %va, flo
323323
%vd = fsub <vscale x 8 x double> %va, %splat
324324
ret <vscale x 8 x double> %vd
325325
}
326+
327+
define <vscale x 1 x double> @vfwsub_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
328+
; CHECK-LABEL: vfwsub_vv_nxv1f64_same_op:
329+
; CHECK: # %bb.0:
330+
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
331+
; CHECK-NEXT: vfwsub.vv v9, v8, v8
332+
; CHECK-NEXT: vmv1r.v v8, v9
333+
; CHECK-NEXT: ret
334+
%vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
335+
%vc = fsub <vscale x 1 x double> %vb, %vb
336+
ret <vscale x 1 x double> %vc
337+
}

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