diff --git a/Rakefile b/Rakefile
index 7d27e9ca8..e2d1a9b54 100755
--- a/Rakefile
+++ b/Rakefile
@@ -388,6 +388,15 @@ file "#{$root}/arch/csr/S/scounteren.yaml" => [
   File.write(t.name, insert_warning(erb.result(binding), t.prerequisites.first))
 end
 
+file "#{$root}/arch/csr/Sscofpmf/scountovf.yaml" => [
+  "#{$root}/arch/csr/Sscofpmf/scountovf.layout",
+  __FILE__
+] do |t|
+  erb = ERB.new(File.read($root / "arch/csr/Sscofpmf/scountovf.layout"), trim_mode: "-")
+  erb.filename = "#{$root}/arch/csr/Sscofpmf/scountovf.layout"
+  File.write(t.name, insert_warning(erb.result(binding), t.prerequisites.first))
+end
+
 file "#{$root}/arch/csr/H/hcounteren.yaml" => [
   "#{$root}/arch/csr/H/hcounteren.layout",
   __FILE__
@@ -421,6 +430,7 @@ namespace :gen do
 
     Rake::Task["#{$root}/arch/csr/I/mcounteren.yaml"].invoke
     Rake::Task["#{$root}/arch/csr/S/scounteren.yaml"].invoke
+    Rake::Task["#{$root}/arch/csr/Sscofpmf/scountovf.yaml"].invoke
     Rake::Task["#{$root}/arch/csr/H/hcounteren.yaml"].invoke
     Rake::Task["#{$root}/arch/csr/Zicntr/mcountinhibit.yaml"].invoke
 
diff --git a/arch/csr/Sscofpmf/scountovf.layout b/arch/csr/Sscofpmf/scountovf.layout
new file mode 100644
index 000000000..b5b677d45
--- /dev/null
+++ b/arch/csr/Sscofpmf/scountovf.layout
@@ -0,0 +1,60 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: csr_schema.json#
+kind: csr
+name: scountovf
+long_name: Supervisor Count Overflow
+address: 0xDA0
+priv_mode: S
+length: 32
+definedBy: Sscofpmf
+description: |
+  A 32-bit read-only
+  register that contains shadow copies of the OF bits in the 29 `mhpmevent` CSRs
+  (`mhpmevent3` - `mhpmevent31`) — where `scountovf` bit X corresponds to `mhpmeventX`.
+
+  This register enables supervisor-level overflow interrupt handler
+  software to quickly and easily determine which counter(s) have overflowed
+  (without needing to make an execution environment call or series of calls ultimately up to M-mode)
+
+  Read access to bit X is subject to the same `mcounteren` (or `mcounteren` and `hcounteren`)
+  CSRs that mediate access to the `hpmcounter` CSRs by S-mode (or VS-mode).
+  In M-mode, `scountovf` bit X is always readable. In S/HS-mode, `scountovf` bit X is readable
+  when `mcounteren` bit X is set, and otherwise reads as zero. Similarly, in VS mode,
+  `scountovf` bit X is readable when `mcounteren` bit X and `hcounteren` bit X are both set, and otherwise reads as zero.
+
+fields:
+  <%- (3..31).each do |of_num| -%>
+    OF<%= of_num %>:
+      alias: mhpmevent<%= of_num %>.OF
+      location: <%= of_num %>
+      description: |
+        [when="HPM_COUNTER_EN[<%= of_num %>] == true"]
+        Shadow copy of mhpmevent<%= of_num %> overflow (OF) bit.
+
+        [when="HPM_COUNTER_EN[<%= of_num %>] == false"]
+        This field is read-only zero because the counter is not enabled.
+      type(): |
+        return HPM_COUNTER_EN[<%= of_num %>] ? CsrFieldType::RO : CsrFieldType::ROH;
+      reset_value(): |
+        return HPM_COUNTER_EN[<%= of_num %>] ? UNDEFINED_LEGAL : 0;
+  <%- end -%>
+
+
+sw_read(): |
+  Bits<32> mask;
+  if (mode() == PrivilegeMode::VS) {
+    # in VS-mode, scountovf.OFX access is determined by mcounteren/hcounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[hcounteren]);
+  } else {
+    # in M-mode and S-mode, scountovf.OFX access is determined by mcounteren/scounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[scounteren]);
+  }
+
+  Bits<32> value =
+  <%- (3..31).each do |num| -%>
+    (CSR[mhpmevent<%= num %>].OF << <%= num %>) |
+  <%- end -%>
+    0;
+
+  return value & mask;
diff --git a/arch/csr/Sscofpmf/scountovf.yaml b/arch/csr/Sscofpmf/scountovf.yaml
new file mode 100644
index 000000000..77331fe80
--- /dev/null
+++ b/arch/csr/Sscofpmf/scountovf.yaml
@@ -0,0 +1,448 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+# WARNING: This file is auto-generated from arch/csr/Sscofpmf/scountovf.layout
+$schema: csr_schema.json#
+kind: csr
+name: scountovf
+long_name: Supervisor Count Overflow
+address: 0xDA0
+priv_mode: S
+length: 32
+definedBy: Sscofpmf
+description: |
+  A 32-bit read-only
+  register that contains shadow copies of the OF bits in the 29 `mhpmevent` CSRs
+  (`mhpmevent3` - `mhpmevent31`) — where `scountovf` bit X corresponds to `mhpmeventX`.
+
+  This register enables supervisor-level overflow interrupt handler
+  software to quickly and easily determine which counter(s) have overflowed
+  (without needing to make an execution environment call or series of calls ultimately up to M-mode)
+
+  Read access to bit X is subject to the same `mcounteren` (or `mcounteren` and `hcounteren`)
+  CSRs that mediate access to the `hpmcounter` CSRs by S-mode (or VS-mode).
+  In M-mode, `scountovf` bit X is always readable. In S/HS-mode, `scountovf` bit X is readable
+  when `mcounteren` bit X is set, and otherwise reads as zero. Similarly, in VS mode,
+  `scountovf` bit X is readable when `mcounteren` bit X and `hcounteren` bit X are both set, and otherwise reads as zero.
+
+fields:
+  OF3:
+    alias: mhpmevent3.OF
+    location: 3
+    description: |
+      [when="HPM_COUNTER_EN[3] == true"]
+      Shadow copy of mhpmevent3 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[3] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[3] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[3] ? UNDEFINED_LEGAL : 0;
+  OF4:
+    alias: mhpmevent4.OF
+    location: 4
+    description: |
+      [when="HPM_COUNTER_EN[4] == true"]
+      Shadow copy of mhpmevent4 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[4] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[4] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[4] ? UNDEFINED_LEGAL : 0;
+  OF5:
+    alias: mhpmevent5.OF
+    location: 5
+    description: |
+      [when="HPM_COUNTER_EN[5] == true"]
+      Shadow copy of mhpmevent5 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[5] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[5] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[5] ? UNDEFINED_LEGAL : 0;
+  OF6:
+    alias: mhpmevent6.OF
+    location: 6
+    description: |
+      [when="HPM_COUNTER_EN[6] == true"]
+      Shadow copy of mhpmevent6 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[6] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[6] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[6] ? UNDEFINED_LEGAL : 0;
+  OF7:
+    alias: mhpmevent7.OF
+    location: 7
+    description: |
+      [when="HPM_COUNTER_EN[7] == true"]
+      Shadow copy of mhpmevent7 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[7] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[7] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[7] ? UNDEFINED_LEGAL : 0;
+  OF8:
+    alias: mhpmevent8.OF
+    location: 8
+    description: |
+      [when="HPM_COUNTER_EN[8] == true"]
+      Shadow copy of mhpmevent8 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[8] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[8] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[8] ? UNDEFINED_LEGAL : 0;
+  OF9:
+    alias: mhpmevent9.OF
+    location: 9
+    description: |
+      [when="HPM_COUNTER_EN[9] == true"]
+      Shadow copy of mhpmevent9 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[9] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[9] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[9] ? UNDEFINED_LEGAL : 0;
+  OF10:
+    alias: mhpmevent10.OF
+    location: 10
+    description: |
+      [when="HPM_COUNTER_EN[10] == true"]
+      Shadow copy of mhpmevent10 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[10] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[10] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[10] ? UNDEFINED_LEGAL : 0;
+  OF11:
+    alias: mhpmevent11.OF
+    location: 11
+    description: |
+      [when="HPM_COUNTER_EN[11] == true"]
+      Shadow copy of mhpmevent11 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[11] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[11] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[11] ? UNDEFINED_LEGAL : 0;
+  OF12:
+    alias: mhpmevent12.OF
+    location: 12
+    description: |
+      [when="HPM_COUNTER_EN[12] == true"]
+      Shadow copy of mhpmevent12 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[12] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[12] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[12] ? UNDEFINED_LEGAL : 0;
+  OF13:
+    alias: mhpmevent13.OF
+    location: 13
+    description: |
+      [when="HPM_COUNTER_EN[13] == true"]
+      Shadow copy of mhpmevent13 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[13] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[13] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[13] ? UNDEFINED_LEGAL : 0;
+  OF14:
+    alias: mhpmevent14.OF
+    location: 14
+    description: |
+      [when="HPM_COUNTER_EN[14] == true"]
+      Shadow copy of mhpmevent14 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[14] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[14] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[14] ? UNDEFINED_LEGAL : 0;
+  OF15:
+    alias: mhpmevent15.OF
+    location: 15
+    description: |
+      [when="HPM_COUNTER_EN[15] == true"]
+      Shadow copy of mhpmevent15 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[15] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[15] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[15] ? UNDEFINED_LEGAL : 0;
+  OF16:
+    alias: mhpmevent16.OF
+    location: 16
+    description: |
+      [when="HPM_COUNTER_EN[16] == true"]
+      Shadow copy of mhpmevent16 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[16] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[16] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[16] ? UNDEFINED_LEGAL : 0;
+  OF17:
+    alias: mhpmevent17.OF
+    location: 17
+    description: |
+      [when="HPM_COUNTER_EN[17] == true"]
+      Shadow copy of mhpmevent17 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[17] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[17] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[17] ? UNDEFINED_LEGAL : 0;
+  OF18:
+    alias: mhpmevent18.OF
+    location: 18
+    description: |
+      [when="HPM_COUNTER_EN[18] == true"]
+      Shadow copy of mhpmevent18 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[18] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[18] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[18] ? UNDEFINED_LEGAL : 0;
+  OF19:
+    alias: mhpmevent19.OF
+    location: 19
+    description: |
+      [when="HPM_COUNTER_EN[19] == true"]
+      Shadow copy of mhpmevent19 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[19] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[19] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[19] ? UNDEFINED_LEGAL : 0;
+  OF20:
+    alias: mhpmevent20.OF
+    location: 20
+    description: |
+      [when="HPM_COUNTER_EN[20] == true"]
+      Shadow copy of mhpmevent20 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[20] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[20] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[20] ? UNDEFINED_LEGAL : 0;
+  OF21:
+    alias: mhpmevent21.OF
+    location: 21
+    description: |
+      [when="HPM_COUNTER_EN[21] == true"]
+      Shadow copy of mhpmevent21 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[21] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[21] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[21] ? UNDEFINED_LEGAL : 0;
+  OF22:
+    alias: mhpmevent22.OF
+    location: 22
+    description: |
+      [when="HPM_COUNTER_EN[22] == true"]
+      Shadow copy of mhpmevent22 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[22] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[22] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[22] ? UNDEFINED_LEGAL : 0;
+  OF23:
+    alias: mhpmevent23.OF
+    location: 23
+    description: |
+      [when="HPM_COUNTER_EN[23] == true"]
+      Shadow copy of mhpmevent23 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[23] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[23] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[23] ? UNDEFINED_LEGAL : 0;
+  OF24:
+    alias: mhpmevent24.OF
+    location: 24
+    description: |
+      [when="HPM_COUNTER_EN[24] == true"]
+      Shadow copy of mhpmevent24 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[24] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[24] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[24] ? UNDEFINED_LEGAL : 0;
+  OF25:
+    alias: mhpmevent25.OF
+    location: 25
+    description: |
+      [when="HPM_COUNTER_EN[25] == true"]
+      Shadow copy of mhpmevent25 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[25] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[25] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[25] ? UNDEFINED_LEGAL : 0;
+  OF26:
+    alias: mhpmevent26.OF
+    location: 26
+    description: |
+      [when="HPM_COUNTER_EN[26] == true"]
+      Shadow copy of mhpmevent26 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[26] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[26] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[26] ? UNDEFINED_LEGAL : 0;
+  OF27:
+    alias: mhpmevent27.OF
+    location: 27
+    description: |
+      [when="HPM_COUNTER_EN[27] == true"]
+      Shadow copy of mhpmevent27 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[27] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[27] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[27] ? UNDEFINED_LEGAL : 0;
+  OF28:
+    alias: mhpmevent28.OF
+    location: 28
+    description: |
+      [when="HPM_COUNTER_EN[28] == true"]
+      Shadow copy of mhpmevent28 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[28] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[28] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[28] ? UNDEFINED_LEGAL : 0;
+  OF29:
+    alias: mhpmevent29.OF
+    location: 29
+    description: |
+      [when="HPM_COUNTER_EN[29] == true"]
+      Shadow copy of mhpmevent29 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[29] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[29] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[29] ? UNDEFINED_LEGAL : 0;
+  OF30:
+    alias: mhpmevent30.OF
+    location: 30
+    description: |
+      [when="HPM_COUNTER_EN[30] == true"]
+      Shadow copy of mhpmevent30 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[30] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[30] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[30] ? UNDEFINED_LEGAL : 0;
+  OF31:
+    alias: mhpmevent31.OF
+    location: 31
+    description: |
+      [when="HPM_COUNTER_EN[31] == true"]
+      Shadow copy of mhpmevent31 overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[31] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[31] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[31] ? UNDEFINED_LEGAL : 0;
+
+sw_read(): |
+  Bits<32> mask;
+  if (mode() == PrivilegeMode::VS) {
+    # in VS-mode, scountovf.OFX access is determined by mcounteren/hcounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[hcounteren]);
+  } else {
+    # in M-mode and S-mode, scountovf.OFX access is determined by mcounteren/scounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[scounteren]);
+  }
+
+  Bits<32> value =
+    (CSR[mhpmevent3].OF << 3) |
+    (CSR[mhpmevent4].OF << 4) |
+    (CSR[mhpmevent5].OF << 5) |
+    (CSR[mhpmevent6].OF << 6) |
+    (CSR[mhpmevent7].OF << 7) |
+    (CSR[mhpmevent8].OF << 8) |
+    (CSR[mhpmevent9].OF << 9) |
+    (CSR[mhpmevent10].OF << 10) |
+    (CSR[mhpmevent11].OF << 11) |
+    (CSR[mhpmevent12].OF << 12) |
+    (CSR[mhpmevent13].OF << 13) |
+    (CSR[mhpmevent14].OF << 14) |
+    (CSR[mhpmevent15].OF << 15) |
+    (CSR[mhpmevent16].OF << 16) |
+    (CSR[mhpmevent17].OF << 17) |
+    (CSR[mhpmevent18].OF << 18) |
+    (CSR[mhpmevent19].OF << 19) |
+    (CSR[mhpmevent20].OF << 20) |
+    (CSR[mhpmevent21].OF << 21) |
+    (CSR[mhpmevent22].OF << 22) |
+    (CSR[mhpmevent23].OF << 23) |
+    (CSR[mhpmevent24].OF << 24) |
+    (CSR[mhpmevent25].OF << 25) |
+    (CSR[mhpmevent26].OF << 26) |
+    (CSR[mhpmevent27].OF << 27) |
+    (CSR[mhpmevent28].OF << 28) |
+    (CSR[mhpmevent29].OF << 29) |
+    (CSR[mhpmevent30].OF << 30) |
+    (CSR[mhpmevent31].OF << 31) |
+    0;
+
+  return value & mask;
diff --git a/arch/csr/Zihpm/mhpmevent10.yaml b/arch/csr/Zihpm/mhpmevent10.yaml
index d5e3511e5..36f9eea40 100644
--- a/arch/csr/Zihpm/mhpmevent10.yaml
+++ b/arch/csr/Zihpm/mhpmevent10.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter10 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter10 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter10 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter10`.
diff --git a/arch/csr/Zihpm/mhpmevent11.yaml b/arch/csr/Zihpm/mhpmevent11.yaml
index 25acd4e78..6e3afb2d5 100644
--- a/arch/csr/Zihpm/mhpmevent11.yaml
+++ b/arch/csr/Zihpm/mhpmevent11.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter11 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter11 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter11 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter11`.
diff --git a/arch/csr/Zihpm/mhpmevent12.yaml b/arch/csr/Zihpm/mhpmevent12.yaml
index 3277d7992..a76e99b41 100644
--- a/arch/csr/Zihpm/mhpmevent12.yaml
+++ b/arch/csr/Zihpm/mhpmevent12.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter12 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter12 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter12 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter12`.
diff --git a/arch/csr/Zihpm/mhpmevent13.yaml b/arch/csr/Zihpm/mhpmevent13.yaml
index 8fe055a95..427c9c0f8 100644
--- a/arch/csr/Zihpm/mhpmevent13.yaml
+++ b/arch/csr/Zihpm/mhpmevent13.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter13 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter13 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter13 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter13`.
diff --git a/arch/csr/Zihpm/mhpmevent14.yaml b/arch/csr/Zihpm/mhpmevent14.yaml
index c4f64bcd0..bee86c431 100644
--- a/arch/csr/Zihpm/mhpmevent14.yaml
+++ b/arch/csr/Zihpm/mhpmevent14.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter14 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter14 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter14 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter14`.
diff --git a/arch/csr/Zihpm/mhpmevent15.yaml b/arch/csr/Zihpm/mhpmevent15.yaml
index bf73956a6..671a01564 100644
--- a/arch/csr/Zihpm/mhpmevent15.yaml
+++ b/arch/csr/Zihpm/mhpmevent15.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter15 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter15 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter15 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter15`.
diff --git a/arch/csr/Zihpm/mhpmevent16.yaml b/arch/csr/Zihpm/mhpmevent16.yaml
index 0f39bfbc9..25b9607bc 100644
--- a/arch/csr/Zihpm/mhpmevent16.yaml
+++ b/arch/csr/Zihpm/mhpmevent16.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter16 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter16 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter16 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter16`.
diff --git a/arch/csr/Zihpm/mhpmevent17.yaml b/arch/csr/Zihpm/mhpmevent17.yaml
index b442d54fb..e71d33f4a 100644
--- a/arch/csr/Zihpm/mhpmevent17.yaml
+++ b/arch/csr/Zihpm/mhpmevent17.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter17 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter17 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter17 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter17`.
diff --git a/arch/csr/Zihpm/mhpmevent18.yaml b/arch/csr/Zihpm/mhpmevent18.yaml
index 95f43e442..a7b6680cf 100644
--- a/arch/csr/Zihpm/mhpmevent18.yaml
+++ b/arch/csr/Zihpm/mhpmevent18.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter18 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter18 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter18 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter18`.
diff --git a/arch/csr/Zihpm/mhpmevent19.yaml b/arch/csr/Zihpm/mhpmevent19.yaml
index 1a1ced791..a01913b16 100644
--- a/arch/csr/Zihpm/mhpmevent19.yaml
+++ b/arch/csr/Zihpm/mhpmevent19.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter19 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter19 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter19 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter19`.
diff --git a/arch/csr/Zihpm/mhpmevent20.yaml b/arch/csr/Zihpm/mhpmevent20.yaml
index 5ec2c960b..9547a0125 100644
--- a/arch/csr/Zihpm/mhpmevent20.yaml
+++ b/arch/csr/Zihpm/mhpmevent20.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter20 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter20 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter20 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter20`.
diff --git a/arch/csr/Zihpm/mhpmevent21.yaml b/arch/csr/Zihpm/mhpmevent21.yaml
index 166aa50f6..de94e1535 100644
--- a/arch/csr/Zihpm/mhpmevent21.yaml
+++ b/arch/csr/Zihpm/mhpmevent21.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter21 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter21 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter21 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter21`.
diff --git a/arch/csr/Zihpm/mhpmevent22.yaml b/arch/csr/Zihpm/mhpmevent22.yaml
index 21f1a3c4b..f44ee9407 100644
--- a/arch/csr/Zihpm/mhpmevent22.yaml
+++ b/arch/csr/Zihpm/mhpmevent22.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter22 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter22 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter22 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter22`.
diff --git a/arch/csr/Zihpm/mhpmevent23.yaml b/arch/csr/Zihpm/mhpmevent23.yaml
index 4e6b623c0..88df06d93 100644
--- a/arch/csr/Zihpm/mhpmevent23.yaml
+++ b/arch/csr/Zihpm/mhpmevent23.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter23 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter23 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter23 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter23`.
diff --git a/arch/csr/Zihpm/mhpmevent24.yaml b/arch/csr/Zihpm/mhpmevent24.yaml
index 89cd20f66..0f0ada8a1 100644
--- a/arch/csr/Zihpm/mhpmevent24.yaml
+++ b/arch/csr/Zihpm/mhpmevent24.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter24 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter24 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter24 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter24`.
diff --git a/arch/csr/Zihpm/mhpmevent25.yaml b/arch/csr/Zihpm/mhpmevent25.yaml
index 4b291b985..97c6e853a 100644
--- a/arch/csr/Zihpm/mhpmevent25.yaml
+++ b/arch/csr/Zihpm/mhpmevent25.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter25 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter25 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter25 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter25`.
diff --git a/arch/csr/Zihpm/mhpmevent26.yaml b/arch/csr/Zihpm/mhpmevent26.yaml
index 0ca5a2c6f..d87816792 100644
--- a/arch/csr/Zihpm/mhpmevent26.yaml
+++ b/arch/csr/Zihpm/mhpmevent26.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter26 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter26 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter26 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter26`.
diff --git a/arch/csr/Zihpm/mhpmevent27.yaml b/arch/csr/Zihpm/mhpmevent27.yaml
index b8e7ba1d1..9b103877e 100644
--- a/arch/csr/Zihpm/mhpmevent27.yaml
+++ b/arch/csr/Zihpm/mhpmevent27.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter27 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter27 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter27 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter27`.
diff --git a/arch/csr/Zihpm/mhpmevent28.yaml b/arch/csr/Zihpm/mhpmevent28.yaml
index f9485190e..0da7dd4d9 100644
--- a/arch/csr/Zihpm/mhpmevent28.yaml
+++ b/arch/csr/Zihpm/mhpmevent28.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter28 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter28 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter28 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter28`.
diff --git a/arch/csr/Zihpm/mhpmevent29.yaml b/arch/csr/Zihpm/mhpmevent29.yaml
index 007d14987..565eeb00c 100644
--- a/arch/csr/Zihpm/mhpmevent29.yaml
+++ b/arch/csr/Zihpm/mhpmevent29.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter29 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter29 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter29 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter29`.
diff --git a/arch/csr/Zihpm/mhpmevent3.yaml b/arch/csr/Zihpm/mhpmevent3.yaml
index bf6237f55..257852678 100644
--- a/arch/csr/Zihpm/mhpmevent3.yaml
+++ b/arch/csr/Zihpm/mhpmevent3.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter3 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter3 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter3 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter3`.
diff --git a/arch/csr/Zihpm/mhpmevent30.yaml b/arch/csr/Zihpm/mhpmevent30.yaml
index 6d5926123..82446915b 100644
--- a/arch/csr/Zihpm/mhpmevent30.yaml
+++ b/arch/csr/Zihpm/mhpmevent30.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter30 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter30 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter30 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter30`.
diff --git a/arch/csr/Zihpm/mhpmevent31.yaml b/arch/csr/Zihpm/mhpmevent31.yaml
index 37b859307..6137f91ae 100644
--- a/arch/csr/Zihpm/mhpmevent31.yaml
+++ b/arch/csr/Zihpm/mhpmevent31.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter31 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter31 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter31 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter31`.
diff --git a/arch/csr/Zihpm/mhpmevent4.yaml b/arch/csr/Zihpm/mhpmevent4.yaml
index 1291ed96f..930ea289b 100644
--- a/arch/csr/Zihpm/mhpmevent4.yaml
+++ b/arch/csr/Zihpm/mhpmevent4.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter4 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter4 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter4 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter4`.
diff --git a/arch/csr/Zihpm/mhpmevent5.yaml b/arch/csr/Zihpm/mhpmevent5.yaml
index bbe2824f5..6cd4dd467 100644
--- a/arch/csr/Zihpm/mhpmevent5.yaml
+++ b/arch/csr/Zihpm/mhpmevent5.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter5 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter5 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter5 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter5`.
diff --git a/arch/csr/Zihpm/mhpmevent6.yaml b/arch/csr/Zihpm/mhpmevent6.yaml
index f4e0b15cb..8143578ab 100644
--- a/arch/csr/Zihpm/mhpmevent6.yaml
+++ b/arch/csr/Zihpm/mhpmevent6.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter6 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter6 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter6 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter6`.
diff --git a/arch/csr/Zihpm/mhpmevent7.yaml b/arch/csr/Zihpm/mhpmevent7.yaml
index c4586b60b..b0a3eb63d 100644
--- a/arch/csr/Zihpm/mhpmevent7.yaml
+++ b/arch/csr/Zihpm/mhpmevent7.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter7 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter7 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter7 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter7`.
diff --git a/arch/csr/Zihpm/mhpmevent8.yaml b/arch/csr/Zihpm/mhpmevent8.yaml
index 349fc9ca3..17d005c3d 100644
--- a/arch/csr/Zihpm/mhpmevent8.yaml
+++ b/arch/csr/Zihpm/mhpmevent8.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter8 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter8 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter8 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter8`.
diff --git a/arch/csr/Zihpm/mhpmevent9.yaml b/arch/csr/Zihpm/mhpmevent9.yaml
index fc947e3e2..28b6bdc02 100644
--- a/arch/csr/Zihpm/mhpmevent9.yaml
+++ b/arch/csr/Zihpm/mhpmevent9.yaml
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter9 does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter9 does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter9 does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter9`.
diff --git a/arch/csr/Zihpm/mhpmeventN.layout b/arch/csr/Zihpm/mhpmeventN.layout
index 0617a27ea..f92f5a89c 100644
--- a/arch/csr/Zihpm/mhpmeventN.layout
+++ b/arch/csr/Zihpm/mhpmeventN.layout
@@ -71,7 +71,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [S, Sscofpmf]
   UINH:
     location: 60
     description: When set, mhpmcounter<%= hpm_num %> does not increment while the hart in operating in U-mode.
@@ -87,7 +88,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [U, Sscofpmf]
   VSINH:
     location: 59
     description: When set, mhpmcounter<%= hpm_num %> does not increment while the hart in operating in VS-mode.
@@ -103,7 +105,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   VUINH:
     location: 58
     description: When set, mhpmcounter<%= hpm_num %> does not increment while the hart in operating in VU-mode.
@@ -119,7 +122,8 @@ fields:
       } else {
         return 0;
       }
-    definedBy: Sscofpmf
+    definedBy:
+      allOf: [H, Sscofpmf]
   EVENT:
     location: 57-0
     description: Event selector for performance counter `mhpmcounter<%= hpm_num %>`.