Verilog-Pipeline

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ControlUnit.v		ControlUnit.v
DecodeUnit.v		DecodeUnit.v
Exec.v		Exec.v
Fetch.v		Fetch.v
Memory.v		Memory.v
Pipeline.v		Pipeline.v
README.md		README.md
Writeback.v		Writeback.v
assembler.cpp		assembler.cpp
assembly.txt		assembly.txt
instruction.mem		instruction.mem
output		output
registers.mem		registers.mem
testbench.v		testbench.v

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