feat: added reserved fields

jriyyya · joydeep049 · commit 6fa08400a58f · 2024-08-17T23:32:29.000+05:30
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
@@ -783,7 +783,7 @@ $[name "fence (instruction)"]
 union clause ast = FENCEI : unit
 
 mapping clause encdec = FENCEI()
-  <-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111
+  <-> reserved_bits_12(ZERO) @ reserved_bits_5(ZERO) @ 0b001 @ reserved_bits_5(ZERO) @ 0b0001111
 
 /* fence.i is a nop for the memory model */
 function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS }
diff --git a/model/riscv_types.sail b/model/riscv_types.sail
@@ -134,6 +134,10 @@ union AccessType ('a : Type) = {
   Execute   : unit
 }
 
+enum reserved_bits_enum = { ZERO }
+mapping reserved_bits_5 : reserved_bits_enum <-> bits(5) = { ZERO <-> 0b00000 }
+mapping reserved_bits_12 : reserved_bits_enum <-> bits(12) = { ZERO <-> 0b000000000000 }
+
 enum word_width = {BYTE, HALF, WORD, DOUBLE}
 
 /* architectural interrupt definitions */

Original file line number	Diff line number	Diff line change
`@@ -134,6 +134,10 @@ union AccessType ('a : Type) = {`
`134`	`134`	`Execute : unit`
`135`	`135`	`}`
`136`	`136`
	`137`	`+enum reserved_bits_enum = { ZERO }`
	`138`	`+mapping reserved_bits_5 : reserved_bits_enum <-> bits(5) = { ZERO <-> 0b00000 }`
	`139`	`+mapping reserved_bits_12 : reserved_bits_enum <-> bits(12) = { ZERO <-> 0b000000000000 }`
	`140`	`+`
`137`	`141`	`enum word_width = {BYTE, HALF, WORD, DOUBLE}`
`138`	`142`
`139`	`143`	`/* architectural interrupt definitions */`