diff --git a/doc/changelog.d/6132.fixed.md b/doc/changelog.d/6132.fixed.md new file mode 100644 index 00000000000..e57a49958b7 --- /dev/null +++ b/doc/changelog.d/6132.fixed.md @@ -0,0 +1 @@ +Output variable with differential pairs \ No newline at end of file diff --git a/src/ansys/aedt/core/application/analysis.py b/src/ansys/aedt/core/application/analysis.py index 8edf351e3fa..5ef3df8725a 100644 --- a/src/ansys/aedt/core/application/analysis.py +++ b/src/ansys/aedt/core/application/analysis.py @@ -352,7 +352,7 @@ def active_setup(self, name): raise ValueError(f"Setup name {name} is invalid.") self._setup = name else: - raise AttributeError("No setup is defined.") + raise AttributeError("No setups defined.") @property def setup_sweeps_names(self): @@ -1470,7 +1470,7 @@ def get_setup(self, name): return self.design_setups[name] @pyaedt_function_handler() - def create_output_variable(self, variable, expression, solution=None, context=None): + def create_output_variable(self, variable, expression, solution=None, context=None, is_differential=False): """Create or modify an output variable. Parameters @@ -1484,6 +1484,9 @@ def create_output_variable(self, variable, expression, solution=None, context=No If `None`, the first available solution is used. Default is `None`. context : list, str, optional Context under which the output variable will produce results. + is_differential : bool, optional + Whether the expression corresponds to a differential pair. + This parameter is only valid for HFSS 3D Layout and Circuit design types. The default value is `False`. Returns ------- @@ -1493,21 +1496,87 @@ def create_output_variable(self, variable, expression, solution=None, context=No References ---------- >>> oModule.CreateOutputVariable + + Examples + -------- + >>> from ansys.aedt.core import Circuit + >>> aedtapp = Circuit() + >>> aedtapp.create_output_variable(variable="output_diff", expression="S(Comm,Diff)", is_differential=True) + >>> aedtapp.create_output_variable(variable="output_terminal", expression="S(1,1)", is_differential=False) """ if context is None: context = [] - if not context and self.solution_type == "Q3D Extractor": - context = ["Context:=", "Original"] - + if not context: + if self.solution_type == "Q3D Extractor": + context = ["Context:=", "Original"] + elif self.design_type == "HFSS 3D Layout Design" and is_differential: + context = [ + "NAME:Context", + "SimValueContext:=", + [ + 3, + 0, + 2, + 0, + False, + False, + -1, + 1, + 0, + 1, + 1, + "", + 0, + 0, + "EnsDiffPairKey", + False, + "1", + "IDIID", + False, + "3", + ], + ] + elif self.design_type == "Circuit Design" and is_differential: + context = [ + "NAME:Context", + "SimValueContext:=", + [ + 3, + 0, + 2, + 0, + False, + False, + -1, + 1, + 0, + 1, + 1, + "", + 0, + 0, + "NUMLEVELS", + False, + "1", + "USE_DIFF_PAIRS", + False, + "1", + ], + ] oModule = self.ooutput_variable if solution is None: + if not self.existing_analysis_sweeps: + raise AEDTRuntimeError("No setups defined.") solution = self.existing_analysis_sweeps[0] if variable in self.output_variables: oModule.EditOutputVariable( variable, expression, variable, solution, self.design_solutions.report_type, context ) else: - oModule.CreateOutputVariable(variable, expression, solution, self.design_solutions.report_type, context) + try: + oModule.CreateOutputVariable(variable, expression, solution, self.design_solutions.report_type, context) + except Exception: + raise AEDTRuntimeError(f"Invalid commands.") return True @pyaedt_function_handler() diff --git a/tests/system/general/test_21_Circuit.py b/tests/system/general/test_21_Circuit.py index 2bfa94060a1..6d003950dec 100644 --- a/tests/system/general/test_21_Circuit.py +++ b/tests/system/general/test_21_Circuit.py @@ -28,6 +28,7 @@ from ansys.aedt.core import Circuit from ansys.aedt.core import generate_unique_name from ansys.aedt.core.generic.settings import is_linux +from ansys.aedt.core.internal.errors import AEDTRuntimeError import pytest from tests import TESTS_GENERAL_PATH @@ -514,8 +515,8 @@ def test_34_activate_variables(self, aedtapp): def test_35_netlist_data_block(self, aedtapp, local_scratch): with open(Path(local_scratch.path) / "lc.net", "w") as f: for i in range(10): - f.write(f"L{i} net_{i} net_{i+1} 1e-9\n") - f.write(f"C{i} net_{i+1} 0 5e-12\n") + f.write(f"L{i} net_{i} net_{i + 1} 1e-9\n") + f.write(f"C{i} net_{i + 1} 0 5e-12\n") assert aedtapp.add_netlist_datablock(Path(local_scratch.path) / "lc.net") aedtapp.modeler.components.create_interface_port("net_0", (0, 0)) aedtapp.modeler.components.create_interface_port("net_10", (0.01, 0)) @@ -535,8 +536,8 @@ def test_37_draw_graphical_primitives(self, aedtapp): def test_38_browse_log_file(self, aedtapp, local_scratch): with open(Path(local_scratch.path) / "lc.net", "w") as f: for i in range(10): - f.write(f"L{i} net_{i} net_{i+1} 1e-9\n") - f.write(f"C{i} net_{i+1} 0 5e-12\n") + f.write(f"L{i} net_{i} net_{i + 1} 1e-9\n") + f.write(f"C{i} net_{i + 1} 0 5e-12\n") aedtapp.modeler.components.create_interface_port("net_0", (0, 0), angle=90) aedtapp.modeler.components.create_interface_port("net_10", (0.01, 0)) lna = aedtapp.create_setup("mylna", aedtapp.SETUPS.NexximLNA) @@ -1032,3 +1033,28 @@ def test_55_get_component_path_and_import_sss_files(self, aedtapp): buffer = ibis_model.buffers["RDQS#"].insert(0.1016, 0.05334, 0.0) assert len(aedtapp.modeler.schematic.components) == 5 assert buffer.component_path + + def test_output_variables(self, circuitprj): + with pytest.raises(AEDTRuntimeError): + circuitprj.create_output_variable( + variable="outputvar_diff2", expression="S(Comm2,Diff2)", is_differential=False + ) + circuitprj.create_setup() + assert circuitprj.create_output_variable(variable="outputvar_terminal", expression="S(1, 1)") + assert len(circuitprj.output_variables) == 1 + assert circuitprj.set_differential_pair( + assignment="Port3", + reference="Port4", + common_mode="Comm2", + differential_mode="Diff2", + common_reference=34, + differential_reference=123, + ) + assert circuitprj.create_output_variable( + variable="outputvar_diff", expression="S(Comm2,Diff2)", is_differential=True + ) + assert len(circuitprj.output_variables) == 2 + with pytest.raises(AEDTRuntimeError): + circuitprj.create_output_variable( + variable="outputvar_diff2", expression="S(Comm2,Diff2)", is_differential=False + ) diff --git a/tests/system/solvers/test_00_analyze.py b/tests/system/solvers/test_00_analyze.py index 6411743e4d9..e6d8f2f3772 100644 --- a/tests/system/solvers/test_00_analyze.py +++ b/tests/system/solvers/test_00_analyze.py @@ -52,7 +52,6 @@ component = "Circ_Patch_5GHz_232.a3dcomp" - test_subfolder = "T00" erl_project_name = "erl_unit_test" com_project_name = "com_unit_test_23r2" @@ -642,3 +641,17 @@ def test_10_export_to_maxwell(self, add_app): app2 = add_app("assm_test2", application=Rmxprt, solution_type="ASSM") app2.import_configuration(config) assert app2.circuit + + def test_output_variables_3dlayout(self, hfss3dl_solved): + hfss3dl_solved.set_differential_pair( + assignment="Port1", reference="Port2", differential_mode="Diff", common_mode="Comm" + ) + assert hfss3dl_solved.create_output_variable( + variable="outputvar_diff", expression="S(Comm,Diff)", is_differential=True + ) + assert hfss3dl_solved.create_output_variable(variable="outputvar_terminal", expression="dB(S(Port1,Port1))") + assert len(hfss3dl_solved.output_variables) == 2 + with pytest.raises(AEDTRuntimeError): + hfss3dl_solved.create_output_variable( + variable="outputvar_diff2", expression="S(Comm,Diff)", is_differential=False + )