diff --git a/doc/changelog.d/6128.fixed.md b/doc/changelog.d/6128.fixed.md
new file mode 100644
index 00000000000..2ad1b24a962
--- /dev/null
+++ b/doc/changelog.d/6128.fixed.md
@@ -0,0 +1 @@
+External circuit import of renamed sources
\ No newline at end of file
diff --git a/src/ansys/aedt/core/maxwell.py b/src/ansys/aedt/core/maxwell.py
index 39bc1dd17ce..47c4edad39e 100644
--- a/src/ansys/aedt/core/maxwell.py
+++ b/src/ansys/aedt/core/maxwell.py
@@ -2053,9 +2053,17 @@ def edit_external_circuit(self, netlist_file_path, schematic_design_name=None, p
             sources_array, sources_type_array = [], []
             for comp in oeditor.GetAllComponents():
                 if "Voltage Source" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"):
-                    comp_id = "V" + comp.split("@")[1].split(";")[1]
+                    name = oeditor.GetPropertyValue("PassedParameterTab", comp, "Name")
+                    if not name:
+                        comp_id = "V" + comp.split("@")[1].split(";")[1]
+                    else:
+                        comp_id = "V" + name
                 elif "Current Source" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"):
-                    comp_id = "I" + comp.split("@")[1].split(";")[1]
+                    name = oeditor.GetPropertyValue("PassedParameterTab", comp, "Name")
+                    if not name:
+                        comp_id = "I" + comp.split("@")[1].split(";")[1]
+                    else:
+                        comp_id = "I" + name
                 else:
                     continue
 
diff --git a/tests/system/general/test_35_MaxwellCircuit.py b/tests/system/general/test_35_MaxwellCircuit.py
index 457707c9c50..6ec29f39877 100644
--- a/tests/system/general/test_35_MaxwellCircuit.py
+++ b/tests/system/general/test_35_MaxwellCircuit.py
@@ -113,6 +113,11 @@ def test_07_export_netlist(self, add_app):
         assert m2d.edit_external_circuit(netlist_file, self.aedtapp.design_name)
         with pytest.raises(AEDTRuntimeError):
             m2d.edit_external_circuit(netlist_file, "invalid")
+        netlist_file_2 = os.path.join(self.local_scratch.path, "export_netlist_2.sph")
+        v_source.parameters["Name"] = "VSource"
+        i_source.parameters["Name"] = "ISource"
+        self.aedtapp.export_netlist_from_schematic(netlist_file_2)
+        assert m2d.edit_external_circuit(netlist_file_2, self.aedtapp.design_name)
 
     def test_08_import_netlist(self):
         self.aedtapp.insert_design("SchematicImport")