From d473c0e8c4dd69301bad09f3e757c61785019812 Mon Sep 17 00:00:00 2001 From: Giulia Malinverno Date: Tue, 29 Apr 2025 15:07:09 +0200 Subject: [PATCH 1/4] fix external_circuit --- src/ansys/aedt/core/maxwell.py | 6 +++--- tests/system/general/test_35_MaxwellCircuit.py | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/ansys/aedt/core/maxwell.py b/src/ansys/aedt/core/maxwell.py index e752c872bec..872820be6dc 100644 --- a/src/ansys/aedt/core/maxwell.py +++ b/src/ansys/aedt/core/maxwell.py @@ -2016,7 +2016,7 @@ def create_external_circuit(self, circuit_design=None): return circuit @pyaedt_function_handler() - def edit_external_circuit(self, netlist_file_path, schematic_design_name, parameters=None): + def edit_external_circuit(self, netlist_file_path, schematic_design_name=None, parameters=None): """ Edit the external circuit for the winding and allow editing of the circuit parameters. @@ -2024,7 +2024,7 @@ def edit_external_circuit(self, netlist_file_path, schematic_design_name, parame ---------- netlist_file_path : str Path to the circuit netlist file. - schematic_design_name : str + schematic_design_name : str, optional Name of the schematic design. parameters : dict, optional Name and value of the circuit parameters. @@ -2039,7 +2039,7 @@ def edit_external_circuit(self, netlist_file_path, schematic_design_name, parame bool ``True`` when successful, ``False`` when failed. """ - if schematic_design_name not in self.design_list: + if schematic_design_name and schematic_design_name not in self.design_list: raise AEDTRuntimeError(f"Schematic design '{schematic_design_name}' is not in design list.") odesign = self.desktop_class.active_design(self.oproject, schematic_design_name) diff --git a/tests/system/general/test_35_MaxwellCircuit.py b/tests/system/general/test_35_MaxwellCircuit.py index 3df6672e2f3..457707c9c50 100644 --- a/tests/system/general/test_35_MaxwellCircuit.py +++ b/tests/system/general/test_35_MaxwellCircuit.py @@ -27,6 +27,7 @@ from ansys.aedt.core import Maxwell2d from ansys.aedt.core import MaxwellCircuit from ansys.aedt.core.generic.constants import SOLUTIONS +from ansys.aedt.core.internal.checks import AEDTRuntimeError import pytest from tests import TESTS_GENERAL_PATH @@ -110,6 +111,8 @@ def test_07_export_netlist(self, add_app): m2d.assign_coil(assignment=["Circle_inner"]) m2d.assign_winding(assignment=["Circle_inner"], winding_type="External", name="Ext_Wdg") assert m2d.edit_external_circuit(netlist_file, self.aedtapp.design_name) + with pytest.raises(AEDTRuntimeError): + m2d.edit_external_circuit(netlist_file, "invalid") def test_08_import_netlist(self): self.aedtapp.insert_design("SchematicImport") From 097c63cc6542700d838d6109e6c5562465b36a09 Mon Sep 17 00:00:00 2001 From: pyansys-ci-bot <92810346+pyansys-ci-bot@users.noreply.github.com> Date: Tue, 29 Apr 2025 13:09:58 +0000 Subject: [PATCH 2/4] chore: adding changelog file 6092.fixed.md [dependabot-skip] --- doc/changelog.d/6092.fixed.md | 1 + 1 file changed, 1 insertion(+) create mode 100644 doc/changelog.d/6092.fixed.md diff --git a/doc/changelog.d/6092.fixed.md b/doc/changelog.d/6092.fixed.md new file mode 100644 index 00000000000..e81ee494597 --- /dev/null +++ b/doc/changelog.d/6092.fixed.md @@ -0,0 +1 @@ +edit_external_circuit \ No newline at end of file From 25b676ef50a9bac61792761ebe031b7b0afb2da6 Mon Sep 17 00:00:00 2001 From: Giulia Malinverno Date: Tue, 29 Apr 2025 15:25:04 +0200 Subject: [PATCH 3/4] improve readability --- src/ansys/aedt/core/maxwell.py | 62 ++++++++++++++++------------------ 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/src/ansys/aedt/core/maxwell.py b/src/ansys/aedt/core/maxwell.py index 872820be6dc..39bc1dd17ce 100644 --- a/src/ansys/aedt/core/maxwell.py +++ b/src/ansys/aedt/core/maxwell.py @@ -2039,42 +2039,40 @@ def edit_external_circuit(self, netlist_file_path, schematic_design_name=None, p bool ``True`` when successful, ``False`` when failed. """ - if schematic_design_name and schematic_design_name not in self.design_list: - raise AEDTRuntimeError(f"Schematic design '{schematic_design_name}' is not in design list.") - - odesign = self.desktop_class.active_design(self.oproject, schematic_design_name) - oeditor = odesign.SetActiveEditor("SchematicEditor") - if is_linux and settings.aedt_version == "2024.1": # pragma: no cover - time.sleep(1) - self.desktop_class.close_windows() - comps = oeditor.GetAllComponents() - sources_array = [] - sources_type_array = [] - for comp in comps: - if "Voltage Source" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"): - comp_id = "V" + comp.split("@")[1].split(";")[1] - elif "Current Source" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"): - comp_id = "I" + comp.split("@")[1].split(";")[1] - else: - continue - sources_array.append(comp_id) - refdes = oeditor.GetPropertyValue("ComponentTab", comp, "RefDes") - comp_instance = oeditor.GetCompInstanceFromRefDes(refdes) - if "DC" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"): - sources_type_array.append(1) - else: - source_type = comp_instance.GetPropHost().GetText("Type") - if source_type == "TIME": + if schematic_design_name: + if schematic_design_name not in self.design_list: + raise AEDTRuntimeError(f"Schematic design '{schematic_design_name}' is not in design list.") + + odesign = self.desktop_class.active_design(self.oproject, schematic_design_name) + oeditor = odesign.SetActiveEditor("SchematicEditor") + + if is_linux and settings.aedt_version == "2024.1": # pragma: no cover + time.sleep(1) + self.desktop_class.close_windows() + + sources_array, sources_type_array = [], [] + for comp in oeditor.GetAllComponents(): + if "Voltage Source" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"): + comp_id = "V" + comp.split("@")[1].split(";")[1] + elif "Current Source" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"): + comp_id = "I" + comp.split("@")[1].split(";")[1] + else: + continue + + sources_array.append(comp_id) + refdes = oeditor.GetPropertyValue("ComponentTab", comp, "RefDes") + comp_instance = oeditor.GetCompInstanceFromRefDes(refdes) + + if "DC" in oeditor.GetPropertyValue("ComponentTab", comp, "Description"): sources_type_array.append(1) - elif source_type == "POS": - sources_type_array.append(2) - elif source_type == "SPEED": - sources_type_array.append(3) + else: + source_type = comp_instance.GetPropHost().GetText("Type") + sources_type_array.append({"TIME": 1, "POS": 2, "SPEED": 3}.get(source_type, 0)) + names = [] values = [] if parameters: - names = list(parameters.keys()) - values = list(parameters.values()) + names, values = list(parameters.keys()), list(parameters.values()) netlist_file_path = "" self.oboundary.EditExternalCircuit(netlist_file_path, sources_array, sources_type_array, names, values) return True From d6ede05962e74292a25cbd21f7cb4e875a153cee Mon Sep 17 00:00:00 2001 From: pyansys-ci-bot <92810346+pyansys-ci-bot@users.noreply.github.com> Date: Tue, 29 Apr 2025 13:33:30 +0000 Subject: [PATCH 4/4] chore: adding changelog file 6092.fixed.md [dependabot-skip] --- doc/changelog.d/6092.fixed.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/changelog.d/6092.fixed.md b/doc/changelog.d/6092.fixed.md index e81ee494597..cf03540943e 100644 --- a/doc/changelog.d/6092.fixed.md +++ b/doc/changelog.d/6092.fixed.md @@ -1 +1 @@ -edit_external_circuit \ No newline at end of file +Schematic name argument optional in edit_external_circuit method \ No newline at end of file