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Implement i16x8.relaxed_q15mulr_s (#4583)
As proposed in WebAssembly/relaxed-simd#40.
1 parent fb2754f commit 094deb0

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11 files changed

+58
-7
lines changed

11 files changed

+58
-7
lines changed

scripts/gen-s-parser.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -533,6 +533,7 @@
533533
("f32x4.relaxed_max", "makeBinary(s, BinaryOp::RelaxedMaxVecF32x4)"),
534534
("f64x2.relaxed_min", "makeBinary(s, BinaryOp::RelaxedMinVecF64x2)"),
535535
("f64x2.relaxed_max", "makeBinary(s, BinaryOp::RelaxedMaxVecF64x2)"),
536+
("i16x8.relaxed_q15mulr_s", "makeBinary(s, BinaryOp::RelaxedQ15MulrSVecI16x8)"),
536537

537538
# reference types instructions
538539
("ref.null", "makeRefNull(s)"),

src/gen-s-parser.inc

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1139,9 +1139,17 @@ switch (op[0]) {
11391139
case 'q':
11401140
if (strcmp(op, "i16x8.q15mulr_sat_s") == 0) { return makeBinary(s, BinaryOp::Q15MulrSatSVecI16x8); }
11411141
goto parse_error;
1142-
case 'r':
1143-
if (strcmp(op, "i16x8.replace_lane") == 0) { return makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI16x8, 8); }
1144-
goto parse_error;
1142+
case 'r': {
1143+
switch (op[8]) {
1144+
case 'l':
1145+
if (strcmp(op, "i16x8.relaxed_q15mulr_s") == 0) { return makeBinary(s, BinaryOp::RelaxedQ15MulrSVecI16x8); }
1146+
goto parse_error;
1147+
case 'p':
1148+
if (strcmp(op, "i16x8.replace_lane") == 0) { return makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI16x8, 8); }
1149+
goto parse_error;
1150+
default: goto parse_error;
1151+
}
1152+
}
11451153
case 's': {
11461154
switch (op[7]) {
11471155
case 'h': {

src/ir/cost.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -493,6 +493,7 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
493493
case NarrowUVecI32x4ToVecI16x8:
494494
case SwizzleVec8x16:
495495
case RelaxedSwizzleVec8x16:
496+
case RelaxedQ15MulrSVecI16x8:
496497
ret = 1;
497498
break;
498499
case InvalidBinary:

src/passes/Print.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1851,6 +1851,9 @@ struct PrintExpressionContents
18511851
case RelaxedSwizzleVec8x16:
18521852
o << "i8x16.relaxed_swizzle";
18531853
break;
1854+
case RelaxedQ15MulrSVecI16x8:
1855+
o << "i16x8.relaxed_q15mulr_s";
1856+
break;
18541857

18551858
case InvalidBinary:
18561859
WASM_UNREACHABLE("unvalid binary operator");

src/wasm-binary.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -887,7 +887,7 @@ enum ASTNodes {
887887

888888
I16x8Abs = 0x80,
889889
I16x8Neg = 0x81,
890-
I16x8Q15mulrSatS = 0x82,
890+
I16x8Q15MulrSatS = 0x82,
891891
I16x8AllTrue = 0x83,
892892
I16x8Bitmask = 0x84,
893893
I16x8NarrowI32x4S = 0x85,
@@ -1037,6 +1037,7 @@ enum ASTNodes {
10371037
F32x4RelaxedMax = 0xe2,
10381038
F64x2RelaxedMin = 0xd4,
10391039
F64x2RelaxedMax = 0xee,
1040+
I16x8RelaxedQ15MulrS = 0x111,
10401041

10411042
// bulk memory opcodes
10421043

src/wasm-interpreter.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -917,6 +917,7 @@ class ExpressionRunner : public OverriddenVisitor<SubType, Flow> {
917917
case AvgrUVecI16x8:
918918
return left.avgrUI16x8(right);
919919
case Q15MulrSatSVecI16x8:
920+
case RelaxedQ15MulrSVecI16x8:
920921
return left.q15MulrSatSI16x8(right);
921922
case ExtMulLowSVecI16x8:
922923
return left.extMulLowSI16x8(right);

src/wasm.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -472,6 +472,7 @@ enum BinaryOp {
472472
RelaxedMaxVecF32x4,
473473
RelaxedMinVecF64x2,
474474
RelaxedMaxVecF64x2,
475+
RelaxedQ15MulrSVecI16x8,
475476

476477
InvalidBinary
477478
};

src/wasm/wasm-binary.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5397,7 +5397,7 @@ bool WasmBinaryBuilder::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
53975397
curr = allocator.alloc<Binary>();
53985398
curr->op = AvgrUVecI16x8;
53995399
break;
5400-
case BinaryConsts::I16x8Q15mulrSatS:
5400+
case BinaryConsts::I16x8Q15MulrSatS:
54015401
curr = allocator.alloc<Binary>();
54025402
curr->op = Q15MulrSatSVecI16x8;
54035403
break;
@@ -5597,6 +5597,10 @@ bool WasmBinaryBuilder::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
55975597
curr = allocator.alloc<Binary>();
55985598
curr->op = RelaxedMaxVecF64x2;
55995599
break;
5600+
case BinaryConsts::I16x8RelaxedQ15MulrS:
5601+
curr = allocator.alloc<Binary>();
5602+
curr->op = RelaxedQ15MulrSVecI16x8;
5603+
break;
56005604
default:
56015605
return false;
56025606
}

src/wasm/wasm-stack.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1666,7 +1666,7 @@ void BinaryInstWriter::visitBinary(Binary* curr) {
16661666
break;
16671667
case Q15MulrSatSVecI16x8:
16681668
o << int8_t(BinaryConsts::SIMDPrefix)
1669-
<< U32LEB(BinaryConsts::I16x8Q15mulrSatS);
1669+
<< U32LEB(BinaryConsts::I16x8Q15MulrSatS);
16701670
break;
16711671
case ExtMulLowSVecI16x8:
16721672
o << int8_t(BinaryConsts::SIMDPrefix)
@@ -1842,6 +1842,10 @@ void BinaryInstWriter::visitBinary(Binary* curr) {
18421842
o << int8_t(BinaryConsts::SIMDPrefix)
18431843
<< U32LEB(BinaryConsts::F64x2RelaxedMax);
18441844
break;
1845+
case RelaxedQ15MulrSVecI16x8:
1846+
o << int8_t(BinaryConsts::SIMDPrefix)
1847+
<< U32LEB(BinaryConsts::I16x8RelaxedQ15MulrS);
1848+
break;
18451849

18461850
case InvalidBinary:
18471851
WASM_UNREACHABLE("invalid binary op");

src/wasm/wasm-validator.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1634,7 +1634,8 @@ void FunctionValidator::visitBinary(Binary* curr) {
16341634
case NarrowSVecI32x4ToVecI16x8:
16351635
case NarrowUVecI32x4ToVecI16x8:
16361636
case SwizzleVec8x16:
1637-
case RelaxedSwizzleVec8x16: {
1637+
case RelaxedSwizzleVec8x16:
1638+
case RelaxedQ15MulrSVecI16x8: {
16381639
shouldBeEqualOrFirstIsUnreachable(
16391640
curr->left->type, Type(Type::v128), curr, "v128 op");
16401641
shouldBeEqualOrFirstIsUnreachable(

test/lit/relaxed-simd.wast

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,25 @@
350350
)
351351
)
352352

353+
;; CHECK-BINARY: (func $i16x8.relaxed_q15mulr_s (param $0 v128) (param $1 v128) (result v128)
354+
;; CHECK-BINARY-NEXT: (i16x8.relaxed_q15mulr_s
355+
;; CHECK-BINARY-NEXT: (local.get $0)
356+
;; CHECK-BINARY-NEXT: (local.get $1)
357+
;; CHECK-BINARY-NEXT: )
358+
;; CHECK-BINARY-NEXT: )
359+
;; CHECK-TEXT: (func $i16x8.relaxed_q15mulr_s (param $0 v128) (param $1 v128) (result v128)
360+
;; CHECK-TEXT-NEXT: (i16x8.relaxed_q15mulr_s
361+
;; CHECK-TEXT-NEXT: (local.get $0)
362+
;; CHECK-TEXT-NEXT: (local.get $1)
363+
;; CHECK-TEXT-NEXT: )
364+
;; CHECK-TEXT-NEXT: )
365+
(func $i16x8.relaxed_q15mulr_s (param $0 v128) (param $1 v128) (result v128)
366+
(i16x8.relaxed_q15mulr_s
367+
(local.get $0)
368+
(local.get $1)
369+
)
370+
)
371+
353372
)
354373
;; CHECK-NODEBUG: (type $v128_v128_v128_=>_v128 (func (param v128 v128 v128) (result v128)))
355374

@@ -481,3 +500,10 @@
481500
;; CHECK-NODEBUG-NEXT: (local.get $1)
482501
;; CHECK-NODEBUG-NEXT: )
483502
;; CHECK-NODEBUG-NEXT: )
503+
504+
;; CHECK-NODEBUG: (func $17 (param $0 v128) (param $1 v128) (result v128)
505+
;; CHECK-NODEBUG-NEXT: (i16x8.relaxed_q15mulr_s
506+
;; CHECK-NODEBUG-NEXT: (local.get $0)
507+
;; CHECK-NODEBUG-NEXT: (local.get $1)
508+
;; CHECK-NODEBUG-NEXT: )
509+
;; CHECK-NODEBUG-NEXT: )

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