From c1745513d6de2794a35dbda5ebd89674b4b2feb9 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Wed, 17 Aug 2022 11:55:01 -0500 Subject: [PATCH 01/16] Add bitfile_version to FPGA class --- python/src/pyripherals/core.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/python/src/pyripherals/core.py b/python/src/pyripherals/core.py index 5e25362..429f3da 100644 --- a/python/src/pyripherals/core.py +++ b/python/src/pyripherals/core.py @@ -432,13 +432,20 @@ class FPGA: """ - def __init__(self, bitfile='default', debug=False): + def __init__(self, bitfile='default', endpoints=None, debug=False): if bitfile == 'default': # Use bitfile from config.yaml fpga_bitfile_path self.bitfile = configs['fpga_bitfile_path'] else: self.bitfile = bitfile + + if endpoints is None: + self.endpoints = Endpoint.get_chip_endpoints('GP') + else: + self.endpoints = endpoints + self.debug = debug + self.bitfile_version = None def init_device(self): @@ -464,7 +471,10 @@ def init_device(self): (self.device_info.deviceMajorVersion, self.device_info.deviceMinorVersion)) print(" Serial Number: %s" % self.device_info.serialNumber) print(" Device ID: %s" % self.device_info.deviceID) - print(" USB Speed %d" % self.device_info.usbSpeed) + print(" USB Speed: %d" % self.device_info.usbSpeed) + + self.bitfile_version = self.read_wire(self.endpoints['BITFILE_VERSION'].address) + print(f"Bitfile Version: {self.bitfile_version}") self.xem.LoadDefaultPLLConfiguration() From d1008b1dd986250b18fd2aab152deb7a65c871f9 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Wed, 17 Aug 2022 11:57:55 -0500 Subject: [PATCH 02/16] Add bitfile_version to .h5 header in DDR3.save_data --- python/src/pyripherals/peripherals/DDR3.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index ff11850..51f988c 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -51,7 +51,7 @@ class DDR3(): """ - def __init__(self, fpga, endpoints=None, data_version='ADC_NO_TIMESTAMPS'): + def __init__(self, fpga, endpoints=None, data_version='TIMESTAMPS'): if endpoints is None: endpoints = Endpoint.get_chip_endpoints('DDR3') self.fpga = fpga @@ -744,6 +744,8 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40): with h5py.File(full_data_name, "w") as file: data_set = file.create_dataset("adc", (self.parameters['adc_channels'], chunk_size), maxshape=( self.parameters['adc_channels'], None)) + data_set.attrs['bitfile_version'] = self.fpga.bitfile_version + while repeat < num_repeats: d, bytes_read_error = self.read_adc(blk_multiples) if self.parameters['data_version'] == 'ADC_NO_TIMESTAMPS': From fd3634700881566538945ae5d0bfdd0bd72cece9 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Fri, 19 Aug 2022 12:57:02 -0500 Subject: [PATCH 03/16] Add str_bitfile_version --- python/src/pyripherals/core.py | 13 ++++++++----- python/src/pyripherals/utils.py | 26 ++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/python/src/pyripherals/core.py b/python/src/pyripherals/core.py index 429f3da..f7aed69 100644 --- a/python/src/pyripherals/core.py +++ b/python/src/pyripherals/core.py @@ -12,7 +12,7 @@ import sys import copy import yaml -from .utils import gen_mask +from .utils import gen_mask, str_bitfile_version from warnings import warn home_dir = os.path.join(os.path.expanduser('~'), '.pyripherals') @@ -443,7 +443,7 @@ def __init__(self, bitfile='default', endpoints=None, debug=False): self.endpoints = Endpoint.get_chip_endpoints('GP') else: self.endpoints = endpoints - + self.debug = debug self.bitfile_version = None @@ -473,11 +473,14 @@ def init_device(self): print(" Device ID: %s" % self.device_info.deviceID) print(" USB Speed: %d" % self.device_info.usbSpeed) - self.bitfile_version = self.read_wire(self.endpoints['BITFILE_VERSION'].address) - print(f"Bitfile Version: {self.bitfile_version}") - self.xem.LoadDefaultPLLConfiguration() + self.bitfile_version = self.read_wire(self.endpoints['BITFILE_VERSION'].address) + if self.bitfile_version < 0: + # An error occurred in the read + self.bitfile_version = 1 # 00.00.01 + print(str_bitfile_version(self.bitfile_version)) + # Download the configuration file. if self.bitfile is not None: if (self.xem.NoError != self.xem.ConfigureFPGA(self.bitfile)): diff --git a/python/src/pyripherals/utils.py b/python/src/pyripherals/utils.py index e88648c..cec99bf 100644 --- a/python/src/pyripherals/utils.py +++ b/python/src/pyripherals/utils.py @@ -491,3 +491,29 @@ def plt_uniques(data, ax=None, block=True): ax.plot(indices, unique_data) plt.show(block=block) + + +def str_bitfile_version(bitfile_version : int) -> str: + """Return the string format of the bitfile version. + + Parameters + ---------- + bitfile_version : int + The bitfile version number in integer form. + + Returns + ------- + str : The string format, decimal separated form of the bitfile version number. + + Examples + -------- + >>> str_bitfile_version(21301) + '02.13.01' + """ + + first = bitfile_version // 10000 + second = (bitfile_version % 10000) // 100 + third = bitfile_version % 100 + pieces = [first, second, third] + pieces_str = ['0' + str(piece) if piece < 10 else str(piece) for piece in pieces] + return '.'.join(pieces_str) From 43917b6c84e980ff82cec1f0ba30a4ed6af1d349 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Fri, 19 Aug 2022 12:59:29 -0500 Subject: [PATCH 04/16] data_to_names accounts for bitfile version --- python/src/pyripherals/peripherals/DDR3.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index fe1850d..a342386 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -602,7 +602,7 @@ def deswizzle(self, d, convert_twos=True): return chan_data - def data_to_names(self, chan_data, old=False): + def data_to_names(self, chan_data, bitfile_version=self.fpga.bitfile_version): """ Put deswizzled data into dictionaries with names that match with the data sources. Complete twos complement conversion where necessary. Check timestamps for skips. @@ -617,8 +617,8 @@ def data_to_names(self, chan_data, old=False): ---------- chan_data : dict of np.arrays data from reading DDR (minimally processed into 2 byte containers) - old : bool - indicates if the chan data is from before the ADS channel B was repositioned to fix synchronization issues + bitfile_version : int + The bitfile version that the .h5 file which held chan_data was created with. Defaults to the bitfile version of the FPGA Returns ------- @@ -657,7 +657,7 @@ def data_to_names(self, chan_data, old=False): # adc_data[i] = custom_signed_to_int(chan_data[i], 16) adc_data[i] = chan_data[i] - if old: + if bitfile_version < 2: # 00.00.02 -> 2 lsb = chan_data[6][0::5].astype(np.uint64) else: lsb = chan_data[7][1::5].astype(np.uint64) @@ -686,7 +686,7 @@ def data_to_names(self, chan_data, old=False): ads = {} ads['A'] = custom_signed_to_int(chan_data[7][0::5], 16) - if old: + if bitfile_version < 2: # 00.00.02 -> 2 ads['B'] = custom_signed_to_int(chan_data[7][1::5], 16) else: ads['B'] = custom_signed_to_int(chan_data[6][0::5], 16) @@ -752,7 +752,7 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40): data_set = file.create_dataset("adc", (self.parameters['adc_channels'], chunk_size), maxshape=( self.parameters['adc_channels'], None)) data_set.attrs['bitfile_version'] = self.fpga.bitfile_version - + while repeat < num_repeats: d, bytes_read_error = self.read_adc(blk_multiples) if self.parameters['data_version'] == 'ADC_NO_TIMESTAMPS': From 4447d24e3548a8ad590021575d410d808bafbc0d Mon Sep 17 00:00:00 2001 From: Ajstros Date: Fri, 19 Aug 2022 13:06:22 -0500 Subject: [PATCH 05/16] Fix data_to_names bitfile_version default value bug --- python/src/pyripherals/peripherals/DDR3.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index a342386..2e84aac 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -602,7 +602,7 @@ def deswizzle(self, d, convert_twos=True): return chan_data - def data_to_names(self, chan_data, bitfile_version=self.fpga.bitfile_version): + def data_to_names(self, chan_data, bitfile_version=None): """ Put deswizzled data into dictionaries with names that match with the data sources. Complete twos complement conversion where necessary. Check timestamps for skips. @@ -641,6 +641,14 @@ def data_to_names(self, chan_data, bitfile_version=self.fpga.bitfile_version): or the timestamp steps are not all the same """ + if bitfile_version is None: + # Old code, hasn't been updated to pass bitfile_version from .h5 file header + # Default to FPGA bitfile version, or version 1 if the FPGA bitfile version is None + if self.fpga.bitfile_version is None: + bitfile_version = 1 + else: + bitfile_version = self.fpga.bitfile_version + # first version of ADC data before DACs + timestamps are stored if self.parameters['data_version'] == 'ADC_NO_TIMESTAMPS': adc_data = chan_data From 48bc8635bcebf77929d9069c5095cbb511928b44 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Fri, 19 Aug 2022 13:11:53 -0500 Subject: [PATCH 06/16] Account for KeyError when accessing BITFILE_VERSION Endpoint --- python/src/pyripherals/core.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/python/src/pyripherals/core.py b/python/src/pyripherals/core.py index f7aed69..542f235 100644 --- a/python/src/pyripherals/core.py +++ b/python/src/pyripherals/core.py @@ -475,9 +475,15 @@ def init_device(self): self.xem.LoadDefaultPLLConfiguration() - self.bitfile_version = self.read_wire(self.endpoints['BITFILE_VERSION'].address) + try: + self.bitfile_version = self.read_wire(self.endpoints['BITFILE_VERSION'].address) + except KeyError: + print('No Endpoint BITFILE_VERSION in Endpoints read from', configs['ep_defines_path']) + # Default to version 1 + self.bitfile_version = 1 if self.bitfile_version < 0: # An error occurred in the read + print('Error reading BITFILE_VERSION endpoint:', self.bitfile_version) self.bitfile_version = 1 # 00.00.01 print(str_bitfile_version(self.bitfile_version)) From 56e3aab8dd0cabd4733a9b5686d1073f9f3ef944 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Fri, 19 Aug 2022 13:15:33 -0500 Subject: [PATCH 07/16] Clarify bitfile version print --- python/src/pyripherals/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/src/pyripherals/core.py b/python/src/pyripherals/core.py index 542f235..0295180 100644 --- a/python/src/pyripherals/core.py +++ b/python/src/pyripherals/core.py @@ -485,7 +485,7 @@ def init_device(self): # An error occurred in the read print('Error reading BITFILE_VERSION endpoint:', self.bitfile_version) self.bitfile_version = 1 # 00.00.01 - print(str_bitfile_version(self.bitfile_version)) + print('Bitfile Version:', str_bitfile_version(self.bitfile_version)) # Download the configuration file. if self.bitfile is not None: From 8879c3683511f1e46371519c6da6891e27fa52cf Mon Sep 17 00:00:00 2001 From: Ajstros Date: Fri, 19 Aug 2022 16:54:01 -0500 Subject: [PATCH 08/16] Fix FIFO index and sample size in DDR3 parameters --- python/src/pyripherals/peripherals/DDR3.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index 2e84aac..1d6db9c 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -57,19 +57,17 @@ def __init__(self, fpga, endpoints=None, data_version='TIMESTAMPS'): self.fpga = fpga self.endpoints = endpoints self.parameters = {'BLOCK_SIZE': 2048, # 1/2 the incoming FIFO depth in bytes (size of the BlockPipeIn) - 'sample_size': 65536, # per channel # number of channels that the DDR is striped between (for DACs) 'channels': 8, 'update_period': 400e-9, # 2.5 MHz -- requires SCLK ~ 50 MHZ - 'port1_index': 0x7f_ff_f8, + 'port1_index': 0x3_7f_ff_f8, 'adc_channels': 8, # number of 2 byte chunks in DDR 'adc_period': 200e-9 } # the index is the DDR address that the circular buffer stops at. # need to write all the way up to this stoping point otherwise the SPI output will glitch - self.parameters['sample_size'] = int( - (self.parameters['port1_index'] + 8)/2) + self.parameters['sample_size'] = int((self.parameters['port1_index'] + 8)/4) self.parameters['data_version'] = data_version # sets deswizzling mode self.data_arrays = [] From 1b7d68fb6e47e0f03c461b23f50a57f1aa5ecead Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 09:30:30 -0500 Subject: [PATCH 09/16] Add append option to DDR3.save_data --- python/src/pyripherals/peripherals/DDR3.py | 26 +++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index 1d6db9c..f2a6c24 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -715,7 +715,7 @@ def data_to_names(self, chan_data, bitfile_version=None): return adc_data, timestamp, dac_data, ads, ads_seq_cnt, error - def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40): + def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append=False): """ read and save DDR data to an hdf file @@ -736,6 +736,17 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40): dictionary of data arrays (keys are channel numbers) """ + + if append: + # If the file doesn't already exist, write a new one + if os.path.exists(os.path.join(data_dir, file_name)): + file_mode = 'a' + else: + file_mode = 'w' + print(f'No existing file found at {os.path.join(data_dir, file_name)}, creating new file') + else: + file_mode = 'w' + chunk_size = int(self.parameters["BLOCK_SIZE"] * blk_multiples / ( self.parameters['adc_channels']*2)) # readings per ADC repeat = 0 @@ -754,10 +765,15 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40): time.sleep(adc_readings*self.parameters['adc_period']) # Save ADC DDR data to a file - with h5py.File(full_data_name, "w") as file: - data_set = file.create_dataset("adc", (self.parameters['adc_channels'], chunk_size), maxshape=( - self.parameters['adc_channels'], None)) - data_set.attrs['bitfile_version'] = self.fpga.bitfile_version + with h5py.File(full_data_name, file_mode) as file: + if append: + data_set = file['adc'] + if data_set.attrs['bitfile_version'] != self.fpga.bitfile_version: + raise Exception(f"File {os.path.join(data_dir, file_name)} bitfile version {data_set.attrs['bitfile_version']} does not match FPGA bitfile version {self.fpga.bitfile_version}") + else: + data_set = file.create_dataset("adc", (self.parameters['adc_channels'], chunk_size), maxshape=( + self.parameters['adc_channels'], None)) + data_set.attrs['bitfile_version'] = self.fpga.bitfile_version while repeat < num_repeats: d, bytes_read_error = self.read_adc(blk_multiples) From 7ca046dc7d69dfe2bb9e80c857434473e7789241 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 09:34:08 -0500 Subject: [PATCH 10/16] Fix append option --- python/src/pyripherals/peripherals/DDR3.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index f2a6c24..e987b66 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -737,13 +737,13 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append """ + # If the file doesn't already exist, write a new one + if os.path.exists(os.path.join(data_dir, file_name)): + print(f'No existing file found at {os.path.join(data_dir, file_name)}, creating new file') + append = False + if append: - # If the file doesn't already exist, write a new one - if os.path.exists(os.path.join(data_dir, file_name)): - file_mode = 'a' - else: - file_mode = 'w' - print(f'No existing file found at {os.path.join(data_dir, file_name)}, creating new file') + file_mode = 'a' else: file_mode = 'w' From cd151313277eb3122ded81b07c38b801b3168bc2 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 09:41:43 -0500 Subject: [PATCH 11/16] Fix append option --- python/src/pyripherals/peripherals/DDR3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index e987b66..baee643 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -738,7 +738,7 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append """ # If the file doesn't already exist, write a new one - if os.path.exists(os.path.join(data_dir, file_name)): + if append and not os.path.exists(os.path.join(data_dir, file_name)): print(f'No existing file found at {os.path.join(data_dir, file_name)}, creating new file') append = False From c69c2db708f0b1c08608185d08f3d60d8e3bd818 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 09:48:32 -0500 Subject: [PATCH 12/16] Fix append option --- python/src/pyripherals/peripherals/DDR3.py | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index baee643..007d239 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -738,9 +738,16 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append """ # If the file doesn't already exist, write a new one - if append and not os.path.exists(os.path.join(data_dir, file_name)): - print(f'No existing file found at {os.path.join(data_dir, file_name)}, creating new file') - append = False + full_data_name = os.path.join(data_dir, file_name) + if append: + if not os.path.exists(full_data_name): + print(f'No existing file found at {full_data_name}, creating new file') + append = False + else: + try: + os.remove(full_data_name) + except OSError: + pass if append: file_mode = 'a' @@ -755,12 +762,6 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append print( f'Reading {adc_readings*2/1024} kB per ADC channel for a total of {adc_readings*self.parameters["adc_period"]*1000} ms of data') - full_data_name = os.path.join(data_dir, file_name) - try: - os.remove(full_data_name) - except OSError: - pass - self.set_adc_read() # enable data into the ADC reading FIFO time.sleep(adc_readings*self.parameters['adc_period']) From 3a9061c17ebf5564ff9ef36047a4abf62e299360 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 09:57:58 -0500 Subject: [PATCH 13/16] Add full data return to DDR3.save_data --- python/src/pyripherals/peripherals/DDR3.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index 007d239..818e9f0 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -732,9 +732,8 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append Returns ------- - chan_data : dict - dictionary of data arrays (keys are channel numbers) - + full_data : np.ndarray + All data in the newly saved h5 file. """ # If the file doesn't already exist, write a new one @@ -800,9 +799,10 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append data_set[:, -chunk_size:] = chan_stack if repeat < num_repeats: data_set.resize(data_set.shape[1] + chunk_size, axis=1) + full_data = data_set[:] print(f'Done with DDR reading: saved as {full_data_name}') - return chan_data + return full_data def read_adc(self, blk_multiples=2048): """ From 3378e0e31d46a84bd641227a239060826a75d012 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 10:06:15 -0500 Subject: [PATCH 14/16] Return new data instead of all data --- python/src/pyripherals/peripherals/DDR3.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index 818e9f0..43a9af3 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -732,8 +732,8 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append Returns ------- - full_data : np.ndarray - All data in the newly saved h5 file. + new_data : np.ndarray + The new data saved in the h5 file. """ # If the file doesn't already exist, write a new one @@ -768,12 +768,14 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append with h5py.File(full_data_name, file_mode) as file: if append: data_set = file['adc'] + new_data_index = data_set.shape[1] + 1 if data_set.attrs['bitfile_version'] != self.fpga.bitfile_version: raise Exception(f"File {os.path.join(data_dir, file_name)} bitfile version {data_set.attrs['bitfile_version']} does not match FPGA bitfile version {self.fpga.bitfile_version}") else: data_set = file.create_dataset("adc", (self.parameters['adc_channels'], chunk_size), maxshape=( self.parameters['adc_channels'], None)) data_set.attrs['bitfile_version'] = self.fpga.bitfile_version + new_data_index = 0 while repeat < num_repeats: d, bytes_read_error = self.read_adc(blk_multiples) @@ -799,10 +801,10 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append data_set[:, -chunk_size:] = chan_stack if repeat < num_repeats: data_set.resize(data_set.shape[1] + chunk_size, axis=1) - full_data = data_set[:] + new_data = data_set[new_data_index:] print(f'Done with DDR reading: saved as {full_data_name}') - return full_data + return new_data def read_adc(self, blk_multiples=2048): """ From 75ed3790b8b957be781a438c6775ff62baf4c2a4 Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 10:09:51 -0500 Subject: [PATCH 15/16] Fix new data return --- python/src/pyripherals/peripherals/DDR3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index 43a9af3..bf4f3be 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -801,7 +801,7 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append data_set[:, -chunk_size:] = chan_stack if repeat < num_repeats: data_set.resize(data_set.shape[1] + chunk_size, axis=1) - new_data = data_set[new_data_index:] + new_data = data_set[:, new_data_index:] print(f'Done with DDR reading: saved as {full_data_name}') return new_data From cdba4d71e57e0abde587d8b57c9895c2fc32c67b Mon Sep 17 00:00:00 2001 From: Ajstros Date: Tue, 23 Aug 2022 13:30:19 -0500 Subject: [PATCH 16/16] Fix new data return --- python/src/pyripherals/peripherals/DDR3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/src/pyripherals/peripherals/DDR3.py b/python/src/pyripherals/peripherals/DDR3.py index bf4f3be..17f5a60 100644 --- a/python/src/pyripherals/peripherals/DDR3.py +++ b/python/src/pyripherals/peripherals/DDR3.py @@ -768,7 +768,7 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40, append with h5py.File(full_data_name, file_mode) as file: if append: data_set = file['adc'] - new_data_index = data_set.shape[1] + 1 + new_data_index = data_set.shape[1] if data_set.attrs['bitfile_version'] != self.fpga.bitfile_version: raise Exception(f"File {os.path.join(data_dir, file_name)} bitfile version {data_set.attrs['bitfile_version']} does not match FPGA bitfile version {self.fpga.bitfile_version}") else: